forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
1431 lines
29 KiB
Diff
1431 lines
29 KiB
Diff
From bb72bb160130c35fa4b7dedd0f881085f0af1313 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 22 Feb 2023 19:15:49 +0000
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Subject: [PATCH 31/32] dts: arm64: mediatek: add MT7988A reference board
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device tree
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Complete device tree include for the MediaTek MT7988A SoC and make use
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of it by adding the device tree of the MediaTek MT7988A Reference Board
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as well as overlays for various options regarding the connected
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network interfaces and storage devices present.
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Available options for GMAC1 (eth0):
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* internal 4-port 1GE switch
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Available options for GMAC2 (eth1):
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* internal 2.5G PHY
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* external MaxLinear 2.5G PHY
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* external Aquantia AQR113C PHY
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* SFP+ cage
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Available options for GMAC3 (eth2):
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* external MaxLinear 2.5G PHY
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* external Aquantia AQR113C PHY
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* SFP+ cage
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Available storage options:
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* eMMC
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* SNFI (ECC-less SPI-NAND with BCH done in SoC)
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* SPI-NAND (with ECC done by the flash die)
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* SPI-NOR
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* SD card
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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--- a/arch/arm64/boot/dts/mediatek/Makefile
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+++ b/arch/arm64/boot/dts/mediatek/Makefile
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@@ -24,6 +24,19 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-b
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb.dtb
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-emmc.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-aqr.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-i2p5g-phy.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-mxl.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth1-sfp.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-aqr.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-mxl.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-eth2-sfp.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-sd.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-snfi-nand.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nand.dtbo
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+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-rfb-spim-nor.dtbo
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-emmc.dtso
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@@ -0,0 +1,33 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2021 MediaTek Inc.
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+ * Author: Frank Wunderlich <frank-w@public-files.de>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&mmc0>;
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+ __overlay__ {
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+ pinctrl-names = "default", "state_uhs";
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+ pinctrl-0 = <&mmc0_pins_emmc_51>;
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+ pinctrl-1 = <&mmc0_pins_emmc_51>;
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+ bus-width = <8>;
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+ max-frequency = <200000000>;
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+ cap-mmc-highspeed;
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+ mmc-hs200-1_8v;
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+ mmc-hs400-1_8v;
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+ hs400-ds-delay = <0x12814>;
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+ vqmmc-supply = <®_1p8v>;
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+ vmmc-supply = <®_3p3v>;
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+ non-removable;
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+ no-sd;
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+ no-sdio;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-aqr.dtso
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@@ -0,0 +1,41 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&mdio_bus>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* external Aquantia AQR113C */
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
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+ reset-assert-us = <100000>;
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+ reset-deassert-us = <221000>;
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&gmac1>;
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+ __overlay__ {
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+ phy-mode = "usxgmii";
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+ phy-connection-type = "usxgmii";
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+ phy = <&phy0>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-i2p5g-phy.dtso
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@@ -0,0 +1,30 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&gmac1>;
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+ __overlay__ {
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+ phy-mode = "internal";
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+ phy-connection-type = "internal";
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+ phy = <&int_2p5g_phy>;
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+ status = "okay";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&int_2p5g_phy>;
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+ __overlay__ {
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+ pinctrl-names = "i2p5gbe-led";
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+ pinctrl-0 = <&i2p5gbe_led0_pins>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-mxl.dtso
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@@ -0,0 +1,39 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&mdio_bus>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* external Maxlinear GPY211C */
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+ phy13: ethernet-phy@13 {
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+ reg = <13>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ phy-mode = "2500base-x";
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&gmac1>;
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+ __overlay__ {
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+ phy-mode = "2500base-x";
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+ phy-connection-type = "2500base-x";
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+ phy = <&phy13>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth1-sfp.dtso
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@@ -0,0 +1,47 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&i2c2>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c2_pins>;
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+ status = "okay";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target-path = "/";
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+ __overlay__ {
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+ sfp_esp1: sfp@1 {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&i2c2>;
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+ mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
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+ los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
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+ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
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+ maximum-power-milliwatt = <3000>;
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&gmac1>;
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+ __overlay__ {
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+ phy-mode = "10gbase-r";
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+ managed = "in-band-status";
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+ sfp = <&sfp_esp1>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-aqr.dtso
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@@ -0,0 +1,41 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&mdio_bus>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* external Aquantia AQR113C */
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+ phy8: ethernet-phy@8 {
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+ reg = <8>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
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+ reset-assert-us = <100000>;
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+ reset-deassert-us = <221000>;
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&gmac2>;
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+ __overlay__ {
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+ phy-mode = "usxgmii";
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+ phy-connection-type = "usxgmii";
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+ phy = <&phy8>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-mxl.dtso
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@@ -0,0 +1,39 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&mdio_bus>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* external Maxlinear GPY211C */
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+ phy5: ethernet-phy@5 {
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+ reg = <5>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ phy-mode = "2500base-x";
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&gmac2>;
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+ __overlay__ {
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+ phy-mode = "2500base-x";
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+ phy-connection-type = "2500base-x";
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+ phy = <&phy5>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-eth2-sfp.dtso
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@@ -0,0 +1,47 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&i2c1>;
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+ __overlay__ {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2c1_pins>;
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+ status = "okay";
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+ };
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+ };
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+
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+ fragment@1 {
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+ target-path = "/";
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+ __overlay__ {
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+ sfp_esp0: sfp@0 {
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+ compatible = "sff,sfp";
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+ i2c-bus = <&i2c1>;
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+ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
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+ los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
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+ tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
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+ maximum-power-milliwatt = <3000>;
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+ };
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+ };
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+ };
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+
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+ fragment@2 {
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+ target = <&gmac2>;
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+ __overlay__ {
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+ phy-mode = "10gbase-r";
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+ managed = "in-band-status";
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+ sfp = <&sfp_esp0>;
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+ status = "okay";
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-sd.dtso
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@@ -0,0 +1,31 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+/*
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+ * Copyright (C) 2023 MediaTek Inc.
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+ * Author: Frank Wunderlich <frank-w@public-files.de>
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@1 {
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+ target-path = <&mmc0>;
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+ __overlay__ {
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+ pinctrl-names = "default", "state_uhs";
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+ pinctrl-0 = <&mmc0_pins_sdcard>;
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+ pinctrl-1 = <&mmc0_pins_sdcard>;
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+ cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
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+ bus-width = <4>;
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+ max-frequency = <52000000>;
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+ cap-sd-highspeed;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_3p3v>;
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+ no-mmc;
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+ status = "okay";
|
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+ };
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+ };
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+};
|
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--- /dev/null
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-snfi-nand.dtso
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@@ -0,0 +1,70 @@
|
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
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+/*
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+ * Copyright (C) 2022 MediaTek Inc.
|
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+ * Author: Sam.Shih <sam.shih@mediatek.com>
|
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+ */
|
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
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+
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+ fragment@0 {
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+ target = <&snand>;
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+ __overlay__ {
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+ status = "okay";
|
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ spi-max-frequency = <52000000>;
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+ spi-tx-bus-width = <4>;
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+ spi-rx-bus-width = <4>;
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+ mediatek,nmbm;
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+ mediatek,bmt-max-ratio = <1>;
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+ mediatek,bmt-max-reserved-blocks = <64>;
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+
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+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "BL2";
|
|
+ reg = <0x00000 0x0100000>;
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ partition@100000 {
|
|
+ label = "u-boot-env";
|
|
+ reg = <0x0100000 0x0080000>;
|
|
+ };
|
|
+
|
|
+ partition@180000 {
|
|
+ label = "Factory";
|
|
+ reg = <0x180000 0x0400000>;
|
|
+ };
|
|
+
|
|
+ partition@580000 {
|
|
+ label = "FIP";
|
|
+ reg = <0x580000 0x0200000>;
|
|
+ };
|
|
+
|
|
+ partition@780000 {
|
|
+ label = "ubi";
|
|
+ reg = <0x780000 0x7080000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&bch>;
|
|
+ __overlay__ {
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand-factory.dtso
|
|
@@ -0,0 +1,87 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
+
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&ubi_part>;
|
|
+
|
|
+ __overlay__ {
|
|
+ volumes {
|
|
+ ubi_factory: ubi-volume-factory {
|
|
+ volname = "factory";
|
|
+
|
|
+ nvmem-layout {
|
|
+ compatible = "fixed-layout";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ eeprom_wmac: eeprom@0 {
|
|
+ reg = <0x0 0x1e00>;
|
|
+ };
|
|
+
|
|
+ gmac2_mac: eeprom@fffee {
|
|
+ reg = <0xfffee 0x6>;
|
|
+ };
|
|
+
|
|
+ gmac1_mac: eeprom@ffff4 {
|
|
+ reg = <0xffff4 0x6>;
|
|
+ };
|
|
+
|
|
+ gmac0_mac: eeprom@ffffa {
|
|
+ reg = <0xffffa 0x6>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@1 {
|
|
+ target = <&pcie0>;
|
|
+ __overlay__ {
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ pcie@0,0 {
|
|
+ reg = <0x0000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ wifi@0,0 {
|
|
+ compatible = "mediatek,mt76";
|
|
+ reg = <0x0000 0 0 0 0>;
|
|
+ nvmem-cell-names = "eeprom";
|
|
+ nvmem-cells = <&eeprom_wmac>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@2 {
|
|
+ target = <&gmac0>;
|
|
+ __overlay__ {
|
|
+ nvmem-cell-names = "mac-address";
|
|
+ nvmem-cells = <&gmac0_mac>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@3 {
|
|
+ target = <&gmac1>;
|
|
+ __overlay__ {
|
|
+ nvmem-cell-names = "mac-address";
|
|
+ nvmem-cells = <&gmac1_mac>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ fragment@4 {
|
|
+ target = <&gmac2>;
|
|
+ __overlay__ {
|
|
+ nvmem-cell-names = "mac-address";
|
|
+ nvmem-cells = <&gmac2_mac>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtso
|
|
@@ -0,0 +1,66 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam.Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spi0>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi0_flash_pins>;
|
|
+ status = "okay";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ spi-tx-bus-width = <4>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ mediatek,nmbm;
|
|
+ mediatek,bmt-max-ratio = <1>;
|
|
+ mediatek,bmt-max-reserved-blocks = <64>;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "BL2";
|
|
+ reg = <0x00000 0x0100000>;
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ partition@100000 {
|
|
+ label = "u-boot-env";
|
|
+ reg = <0x0100000 0x0080000>;
|
|
+ };
|
|
+
|
|
+ partition@180000 {
|
|
+ label = "Factory";
|
|
+ reg = <0x180000 0x0400000>;
|
|
+ };
|
|
+
|
|
+ partition@580000 {
|
|
+ label = "FIP";
|
|
+ reg = <0x580000 0x0200000>;
|
|
+ };
|
|
+
|
|
+ partition@780000 {
|
|
+ label = "ubi";
|
|
+ reg = <0x780000 0x7080000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nor.dtso
|
|
@@ -0,0 +1,61 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam.Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+/plugin/;
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
|
+
|
|
+ fragment@0 {
|
|
+ target = <&spi2>;
|
|
+ __overlay__ {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi2_flash_pins>;
|
|
+ status = "okay";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ flash@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "jedec,spi-nor";
|
|
+ spi-cal-enable;
|
|
+ spi-cal-mode = "read-data";
|
|
+ spi-cal-datalen = <7>;
|
|
+ spi-cal-data = /bits/ 8 <
|
|
+ 0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
|
|
+ spi-cal-addrlen = <1>;
|
|
+ spi-cal-addr = /bits/ 32 <0x0>;
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ spi-tx-bus-width = <4>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "BL2";
|
|
+ reg = <0x0 0x40000>;
|
|
+ };
|
|
+ partition@40000 {
|
|
+ label = "u-boot-env";
|
|
+ reg = <0x40000 0x10000>;
|
|
+ };
|
|
+ partition@50000 {
|
|
+ label = "Factory";
|
|
+ reg = <0x50000 0x200000>;
|
|
+ };
|
|
+ partition@250000 {
|
|
+ label = "FIP";
|
|
+ reg = <0x250000 0x80000>;
|
|
+ };
|
|
+ partition@2D0000 {
|
|
+ label = "firmware";
|
|
+ reg = <0x2d0000 0x1d30000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dts
|
|
@@ -0,0 +1,470 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam.Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include <dt-bindings/pinctrl/mt65xx.h>
|
|
+#include <dt-bindings/leds/common.h>
|
|
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
|
|
+
|
|
+#include "mt7988a.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "MediaTek MT7988A Reference Board";
|
|
+ compatible = "mediatek,mt7988a-rfb",
|
|
+ "mediatek,mt7988";
|
|
+
|
|
+ chosen {
|
|
+ bootargs = "console=ttyS0,115200n1 loglevel=8 \
|
|
+ earlycon=uart8250,mmio32,0x11000000 \
|
|
+ pci=pcie_bus_perf";
|
|
+ };
|
|
+
|
|
+ memory {
|
|
+ reg = <0 0x40000000 0 0x40000000>;
|
|
+ };
|
|
+
|
|
+ reg_1p8v: regulator-1p8v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-1.8V";
|
|
+ regulator-min-microvolt = <1800000>;
|
|
+ regulator-max-microvolt = <1800000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-3.3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+ð {
|
|
+ pinctrl-0 = <&mdio0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+};
|
|
+
|
|
+&gmac0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&cpu0 {
|
|
+ proc-supply = <&rt5190_buck3>;
|
|
+};
|
|
+
|
|
+&cpu1 {
|
|
+ proc-supply = <&rt5190_buck3>;
|
|
+};
|
|
+
|
|
+&cpu2 {
|
|
+ proc-supply = <&rt5190_buck3>;
|
|
+};
|
|
+
|
|
+&cpu3 {
|
|
+ proc-supply = <&rt5190_buck3>;
|
|
+};
|
|
+
|
|
+&cci {
|
|
+ proc-supply = <&rt5190_buck3>;
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&switch {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gsw_phy0 {
|
|
+ pinctrl-names = "gbe-led";
|
|
+ pinctrl-0 = <&gbe0_led0_pins>;
|
|
+};
|
|
+
|
|
+&gsw_phy0_led0 {
|
|
+ status = "okay";
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+};
|
|
+
|
|
+&gsw_port0 {
|
|
+ label = "lan0";
|
|
+};
|
|
+
|
|
+&gsw_phy1 {
|
|
+ pinctrl-names = "gbe-led";
|
|
+ pinctrl-0 = <&gbe1_led0_pins>;
|
|
+};
|
|
+
|
|
+&gsw_phy1_led0 {
|
|
+ status = "okay";
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+};
|
|
+
|
|
+&gsw_port1 {
|
|
+ label = "lan1";
|
|
+};
|
|
+
|
|
+&gsw_phy2 {
|
|
+ pinctrl-names = "gbe-led";
|
|
+ pinctrl-0 = <&gbe2_led0_pins>;
|
|
+};
|
|
+
|
|
+&gsw_phy2_led0 {
|
|
+ status = "okay";
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+};
|
|
+
|
|
+&gsw_port2 {
|
|
+ label = "lan2";
|
|
+};
|
|
+
|
|
+&gsw_phy3 {
|
|
+ pinctrl-names = "gbe-led";
|
|
+ pinctrl-0 = <&gbe3_led0_pins>;
|
|
+};
|
|
+
|
|
+&gsw_phy3_led0 {
|
|
+ status = "okay";
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ color = <LED_COLOR_ID_GREEN>;
|
|
+};
|
|
+
|
|
+&gsw_port3 {
|
|
+ label = "lan3";
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c0_pins>;
|
|
+ status = "okay";
|
|
+
|
|
+ rt5190a_64: rt5190a@64 {
|
|
+ compatible = "richtek,rt5190a";
|
|
+ reg = <0x64>;
|
|
+ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
|
|
+ vin2-supply = <&rt5190_buck1>;
|
|
+ vin3-supply = <&rt5190_buck1>;
|
|
+ vin4-supply = <&rt5190_buck1>;
|
|
+
|
|
+ regulators {
|
|
+ rt5190_buck1: buck1 {
|
|
+ regulator-name = "rt5190a-buck1";
|
|
+ regulator-min-microvolt = <5090000>;
|
|
+ regulator-max-microvolt = <5090000>;
|
|
+ regulator-allowed-modes =
|
|
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+ buck2 {
|
|
+ regulator-name = "vcore";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <1400000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+ rt5190_buck3: buck3 {
|
|
+ regulator-name = "vproc";
|
|
+ regulator-min-microvolt = <600000>;
|
|
+ regulator-max-microvolt = <1400000>;
|
|
+ regulator-boot-on;
|
|
+ };
|
|
+ buck4 {
|
|
+ regulator-name = "rt5190a-buck4";
|
|
+ regulator-min-microvolt = <850000>;
|
|
+ regulator-max-microvolt = <850000>;
|
|
+ regulator-allowed-modes =
|
|
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+ ldo {
|
|
+ regulator-name = "rt5190a-ldo";
|
|
+ regulator-min-microvolt = <1200000>;
|
|
+ regulator-max-microvolt = <1200000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&pcie0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pcie2 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&pcie3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pio {
|
|
+ mdio0_pins: mdio0-pins {
|
|
+ mux {
|
|
+ function = "eth";
|
|
+ groups = "mdc_mdio0";
|
|
+ };
|
|
+
|
|
+ conf {
|
|
+ groups = "mdc_mdio0";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe0_led0_pins: gbe0-led0-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe0_led0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe1_led0_pins: gbe1-led0-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe1_led0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe2_led0_pins: gbe2-led0-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe2_led0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe3_led0_pins: gbe3-led0-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe3_led0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe0_led1_pins: gbe0-led1-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe0_led1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe1_led1_pins: gbe1-led1-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe1_led1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe2_led1_pins: gbe2-led1-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe2_led1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gbe3_led1_pins: gbe3-led1-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "gbe3_led1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c0_pins: i2c0-g0-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c0_1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_pins: i2c1-g0-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c1_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c1_sfp_pins: i2c1-sfp-g0-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c1_sfp";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_0_pins: i2c2-g0-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c2_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2c2_1_pins: i2c2-g1-pins {
|
|
+ mux {
|
|
+ function = "i2c";
|
|
+ groups = "i2c2_1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2p5gbe_led0_pins: 2p5gbe-led0-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "2p5gbe_led0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ i2p5gbe_led1_pins: 2p5gbe-led1-pins {
|
|
+ mux {
|
|
+ function = "led";
|
|
+ groups = "2p5gbe_led1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc0_pins_emmc_51: mmc0-emmc-51-pins {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "emmc_51";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc0_pins_sdcard: mmc0-sdcard-pins {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "sdcard";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi0_pins: spi0-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi0_flash_pins: spi0-flash-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi2_pins: spi2-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi2_flash_pins: spi2-flash-pins {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi2", "spi2_wp_hold";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart0_pins: uart0-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_0_pins: uart1-0-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_1_pins: uart1-1-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_2_pins: uart1-2-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_2_lite_pins: uart1-2-lite-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_2_lite";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart2_pins: uart2-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart2_0_pins: uart2-0-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart2_0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart2_1_pins: uart2-1-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart2_1";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart2_2_pins: uart2-2-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart2_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart2_3_pins: uart2-3-pins {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart2_3";
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&ssusb0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ssusb1 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&tphy {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&serial0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&watchdog {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&xsphy {
|
|
+ status = "okay";
|
|
+};
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
|
|
@@ -193,7 +193,7 @@
|
|
};
|
|
|
|
pio: pinctrl@1001f000 {
|
|
- compatible = "mediatek,mt7988-pinctrl";
|
|
+ compatible = "mediatek,mt7988-pinctrl", "syscon";
|
|
reg = <0 0x1001f000 0 0x1000>,
|
|
<0 0x11c10000 0 0x1000>,
|
|
<0 0x11d00000 0 0x1000>,
|
|
@@ -212,6 +212,13 @@
|
|
interrupt-parent = <&gic>;
|
|
#interrupt-cells = <2>;
|
|
|
|
+ snfi_pins: snfi-pins {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "snfi";
|
|
+ };
|
|
+ };
|
|
+
|
|
pcie0_pins: pcie0-pins {
|
|
mux {
|
|
function = "pcie";
|
|
@@ -278,6 +285,60 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ sgmiisys0: syscon@10060000 {
|
|
+ compatible = "mediatek,mt7988-sgmiisys",
|
|
+ "mediatek,mt7988-sgmiisys0",
|
|
+ "syscon",
|
|
+ "simple-mfd";
|
|
+ reg = <0 0x10060000 0 0x1000>;
|
|
+ resets = <&watchdog 1>;
|
|
+ #clock-cells = <1>;
|
|
+
|
|
+ sgmiipcs0: pcs {
|
|
+ compatible = "mediatek,mt7988-sgmii";
|
|
+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
|
|
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
|
|
+ <&sgmiisys0 CLK_SGM0_RX_EN>;
|
|
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
|
|
+ #pcs-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sgmiisys1: syscon@10070000 {
|
|
+ compatible = "mediatek,mt7988-sgmiisys",
|
|
+ "mediatek,mt7988-sgmiisys1",
|
|
+ "syscon",
|
|
+ "simple-mfd";
|
|
+ reg = <0 0x10070000 0 0x1000>;
|
|
+ resets = <&watchdog 2>;
|
|
+ #clock-cells = <1>;
|
|
+
|
|
+ sgmiipcs1: pcs {
|
|
+ compatible = "mediatek,mt7988-sgmii";
|
|
+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
|
|
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
|
|
+ <&sgmiisys1 CLK_SGM1_RX_EN>;
|
|
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
|
|
+ #pcs-cells = <0>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usxgmiisys0: pcs@10080000 {
|
|
+ compatible = "mediatek,mt7988-usxgmiisys";
|
|
+ reg = <0 0x10080000 0 0x1000>;
|
|
+ resets = <&watchdog 12>;
|
|
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
|
|
+ #pcs-cells = <0>;
|
|
+ };
|
|
+
|
|
+ usxgmiisys1: pcs@10081000 {
|
|
+ compatible = "mediatek,mt7988-usxgmiisys";
|
|
+ reg = <0 0x10081000 0 0x1000>;
|
|
+ resets = <&watchdog 13>;
|
|
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
|
|
+ #pcs-cells = <0>;
|
|
+ };
|
|
+
|
|
mcusys: mcusys@100e0000 {
|
|
compatible = "mediatek,mt7988-mcusys", "syscon";
|
|
reg = <0 0x100e0000 0 0x1000>;
|
|
@@ -319,6 +380,32 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ snand: spi@11001000 {
|
|
+ compatible = "mediatek,mt7986-snand";
|
|
+ reg = <0 0x11001000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_SPINFI>,
|
|
+ <&infracfg CLK_INFRA_NFI>,
|
|
+ <&infracfg CLK_INFRA_66M_NFI_HCK>;
|
|
+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
|
+ nand-ecc-engine = <&bch>;
|
|
+ mediatek,quad-spi;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&snfi_pins>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ bch: ecc@11002000 {
|
|
+ compatible = "mediatek,mt7686-ecc";
|
|
+ reg = <0 0x11002000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_NFI>;
|
|
+ clock-names = "nfiecc_clk";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
i2c0: i2c@11003000 {
|
|
compatible = "mediatek,mt7981-i2c";
|
|
reg = <0 0x11003000 0 0x1000>,
|
|
@@ -425,7 +512,7 @@
|
|
<0 0x0f0f0018 0 0x20>;
|
|
};
|
|
|
|
- usb@11190000 {
|
|
+ ssusb0: usb@11190000 {
|
|
compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
|
|
reg = <0 0x11190000 0 0x2e00>,
|
|
<0 0x11193e00 0 0x0100>;
|
|
@@ -459,6 +546,35 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ afe: audio-controller@11210000 {
|
|
+ compatible = "mediatek,mt79xx-audio";
|
|
+ reg = <0 0x11210000 0 0x9000>;
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
|
|
+ <&infracfg CLK_INFRA_AUD_26M>,
|
|
+ <&infracfg CLK_INFRA_AUD_L>,
|
|
+ <&infracfg CLK_INFRA_AUD_AUD>,
|
|
+ <&infracfg CLK_INFRA_AUD_EG2>,
|
|
+ <&topckgen CLK_TOP_AUD_SEL>,
|
|
+ <&topckgen CLK_TOP_AUD_I2S_M>;
|
|
+ clock-names = "aud_bus_ck",
|
|
+ "aud_26m_ck",
|
|
+ "aud_l_ck",
|
|
+ "aud_aud_ck",
|
|
+ "aud_eg2_ck",
|
|
+ "aud_sel",
|
|
+ "aud_i2s_m";
|
|
+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
|
+ <&topckgen CLK_TOP_A1SYS_SEL>,
|
|
+ <&topckgen CLK_TOP_AUD_L_SEL>,
|
|
+ <&topckgen CLK_TOP_A_TUNER_SEL>;
|
|
+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
|
|
+ <&topckgen CLK_TOP_APLL2_D4>,
|
|
+ <&apmixedsys CLK_APMIXED_APLL2>,
|
|
+ <&topckgen CLK_TOP_APLL2_D4>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7988-mmc";
|
|
reg = <0 0x11230000 0 0x1000>,
|
|
@@ -721,6 +837,10 @@
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
+ cpufreq_calibration: calib@278 {
|
|
+ reg = <0x278 0x1>;
|
|
+ };
|
|
+
|
|
lvts_calibration: calib@918 {
|
|
reg = <0x918 0x28>;
|
|
};
|
|
@@ -984,12 +1104,16 @@
|
|
gmac1: mac@1 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <1>;
|
|
+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
|
|
+ phys = <&xfi_tphy1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac2: mac@2 {
|
|
compatible = "mediatek,eth-mac";
|
|
reg = <2>;
|
|
+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
|
|
+ phys = <&xfi_tphy0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
@@ -1002,9 +1126,37 @@
|
|
reg = <15>;
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
phy-mode = "internal";
|
|
+
|
|
+ leds {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ i2p5gbe_led0: i2p5gbe-led0@0 {
|
|
+ reg = <0>;
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ i2p5gbe_led1: i2p5gbe-led1@1 {
|
|
+ reg = <1>;
|
|
+ function = LED_FUNCTION_LAN;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
};
|
|
+
|
|
+ crypto: crypto@15600000 {
|
|
+ compatible = "inside-secure,safexcel-eip197b";
|
|
+ reg = <0 0x15600000 0 0x180000>;
|
|
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
|
+ status = "okay";
|
|
+ };
|
|
};
|
|
|
|
thermal-zones {
|