forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
214 lines
7.2 KiB
Diff
214 lines
7.2 KiB
Diff
From patchwork Sun May 11 14:19:24 2025
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
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X-Patchwork-Id: 14084161
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From: Frank Wunderlich <linux@fw-web.de>
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To: Andrew Lunn <andrew@lunn.ch>,
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Vladimir Oltean <olteanv@gmail.com>,
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"David S. Miller" <davem@davemloft.net>,
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Eric Dumazet <edumazet@google.com>,
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Jakub Kicinski <kuba@kernel.org>,
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Paolo Abeni <pabeni@redhat.com>,
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Rob Herring <robh@kernel.org>,
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Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Conor Dooley <conor+dt@kernel.org>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Subject: [PATCH v1 08/14] arm64: dts: mediatek: mt7988: add basic
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ethernet-nodes
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Date: Sun, 11 May 2025 16:19:24 +0200
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Message-ID: <20250511141942.10284-9-linux@fw-web.de>
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X-Mailer: git-send-email 2.43.0
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In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
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References: <20250511141942.10284-1-linux@fw-web.de>
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X-BeenThere: linux-mediatek@lists.infradead.org
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Precedence: list
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List-Post: <mailto:linux-mediatek@lists.infradead.org>
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List-Help: <mailto:linux-mediatek-request@lists.infradead.org?subject=help>
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List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mediatek>,
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<mailto:linux-mediatek-request@lists.infradead.org?subject=subscribe>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
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=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
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netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
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Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
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DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
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Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
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Felix Fietkau <nbd@nbd.name>
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Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
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Errors-To:
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linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
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From: Frank Wunderlich <frank-w@public-files.de>
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Add basic ethernet related nodes.
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Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked
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later when driver is merged.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 124 +++++++++++++++++++++-
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1 file changed, 121 insertions(+), 3 deletions(-)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -686,7 +686,28 @@
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};
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};
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- clock-controller@11f40000 {
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+ xfi_tphy0: phy@11f20000 {
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+ compatible = "mediatek,mt7988-xfi-tphy";
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+ reg = <0 0x11f20000 0 0x10000>;
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+ resets = <&watchdog 14>;
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+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
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+ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
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+ clock-names = "xfipll", "topxtal";
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+ mediatek,usxgmii-performance-errata;
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+ #phy-cells = <0>;
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+ };
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+
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+ xfi_tphy1: phy@11f30000 {
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+ compatible = "mediatek,mt7988-xfi-tphy";
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+ reg = <0 0x11f30000 0 0x10000>;
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+ resets = <&watchdog 15>;
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+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
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+ <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
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+ clock-names = "xfipll", "topxtal";
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+ #phy-cells = <0>;
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+ };
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+
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+ xfi_pll: clock-controller@11f40000 {
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compatible = "mediatek,mt7988-xfi-pll";
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reg = <0 0x11f40000 0 0x1000>;
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resets = <&watchdog 16>;
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@@ -720,19 +741,116 @@
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};
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};
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- clock-controller@15000000 {
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+ ethsys: clock-controller@15000000 {
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compatible = "mediatek,mt7988-ethsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- clock-controller@15031000 {
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+ ethwarp: clock-controller@15031000 {
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compatible = "mediatek,mt7988-ethwarp";
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reg = <0 0x15031000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ eth: ethernet@15100000 {
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+ compatible = "mediatek,mt7988-eth";
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+ reg = <0 0x15100000 0 0x80000>,
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+ <0 0x15400000 0 0x200000>;
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+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>,
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+ <ðsys CLK_ETHDMA_FE_EN>,
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+ <ðsys CLK_ETHDMA_GP2_EN>,
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+ <ðsys CLK_ETHDMA_GP1_EN>,
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+ <ðsys CLK_ETHDMA_GP3_EN>,
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+ <ðwarp CLK_ETHWARP_WOCPU2_EN>,
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+ <ðwarp CLK_ETHWARP_WOCPU1_EN>,
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+ <ðwarp CLK_ETHWARP_WOCPU0_EN>,
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+ <ðsys CLK_ETHDMA_ESW_EN>,
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+ <&topckgen CLK_TOP_ETH_GMII_SEL>,
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+ <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
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+ <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
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+ <&topckgen CLK_TOP_ETH_SYS_SEL>,
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+ <&topckgen CLK_TOP_ETH_XGMII_SEL>,
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+ <&topckgen CLK_TOP_ETH_MII_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_500M_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_WARP_SEL>,
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+ <ðsys CLK_ETHDMA_XGP1_EN>,
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+ <ðsys CLK_ETHDMA_XGP2_EN>,
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+ <ðsys CLK_ETHDMA_XGP3_EN>;
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+ clock-names = "crypto", "fe", "gp2", "gp1",
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+ "gp3",
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+ "ethwarp_wocpu2", "ethwarp_wocpu1",
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+ "ethwarp_wocpu0", "esw", "top_eth_gmii_sel",
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+ "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
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+ "top_eth_sys_sel", "top_eth_xgmii_sel",
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+ "top_eth_mii_sel", "top_netsys_sel",
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+ "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
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+ "top_netsys_sync_250m_sel",
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+ "top_netsys_ppefb_250m_sel",
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+ "top_netsys_warp_sel","xgp1", "xgp2", "xgp3";
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+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
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+ <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
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+ <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
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+ <&topckgen CLK_TOP_SGM_0_SEL>,
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+ <&topckgen CLK_TOP_SGM_1_SEL>;
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+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
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+ <&topckgen CLK_TOP_NET1PLL_D4>,
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+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
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+ <&topckgen CLK_TOP_NET1PLL_D8_D4>,
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+ <&apmixedsys CLK_APMIXED_SGMPLL>,
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+ <&apmixedsys CLK_APMIXED_SGMPLL>;
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+ mediatek,ethsys = <ðsys>;
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+ mediatek,infracfg = <&topmisc>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ gmac0: mac@0 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <0>;
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+ phy-mode = "internal";
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+
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+ fixed-link {
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+ speed = <10000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
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+ gmac1: mac@1 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <1>;
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+ status = "disabled";
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+ };
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+
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+ gmac2: mac@2 {
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+ compatible = "mediatek,eth-mac";
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+ reg = <2>;
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+ status = "disabled";
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+ };
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+
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+ mdio_bus: mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* internal 2.5G PHY */
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+ int_2p5g_phy: ethernet-phy@f {
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+ reg = <15>;
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ phy-mode = "internal";
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+ };
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+ };
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+ };
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};
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thermal-zones {
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