forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
113 lines
4.2 KiB
Diff
113 lines
4.2 KiB
Diff
From patchwork Sun May 11 14:19:20 2025
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X-Patchwork-Submitter: Frank Wunderlich <linux@fw-web.de>
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X-Patchwork-Id: 14084127
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From: Frank Wunderlich <linux@fw-web.de>
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To: Andrew Lunn <andrew@lunn.ch>,
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Vladimir Oltean <olteanv@gmail.com>,
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"David S. Miller" <davem@davemloft.net>,
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Eric Dumazet <edumazet@google.com>,
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Jakub Kicinski <kuba@kernel.org>,
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Paolo Abeni <pabeni@redhat.com>,
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Rob Herring <robh@kernel.org>,
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Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Conor Dooley <conor+dt@kernel.org>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Subject: [PATCH v1 04/14] arm64: dts: mediatek: mt7988: add spi controllers
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Date: Sun, 11 May 2025 16:19:20 +0200
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Message-ID: <20250511141942.10284-5-linux@fw-web.de>
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In-Reply-To: <20250511141942.10284-1-linux@fw-web.de>
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References: <20250511141942.10284-1-linux@fw-web.de>
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Cc: devicetree@vger.kernel.org, Landen Chao <Landen.Chao@mediatek.com>,
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=?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
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netdev@vger.kernel.org, Sean Wang <sean.wang@mediatek.com>,
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Daniel Golle <daniel@makrotopia.org>, linux-kernel@vger.kernel.org,
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DENG Qingfang <dqfext@gmail.com>, linux-mediatek@lists.infradead.org,
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Lorenzo Bianconi <lorenzo@kernel.org>, linux-arm-kernel@lists.infradead.org,
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Felix Fietkau <nbd@nbd.name>
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Sender: "Linux-mediatek" <linux-mediatek-bounces@lists.infradead.org>
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Errors-To:
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linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org
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From: Frank Wunderlich <frank-w@public-files.de>
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Add SPI controllers for mt7988.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++++
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1 file changed, 45 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -311,6 +311,51 @@
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status = "disabled";
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};
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+ spi0: spi@11007000 {
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+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
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+ reg = <0 0x11007000 0 0x100>;
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_104M_SPI0>,
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+ <&infracfg CLK_INFRA_66M_SPI0_HCK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk",
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+ "hclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@11008000 {
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+ compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm";
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+ reg = <0 0x11008000 0 0x100>;
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+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
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+ <&infracfg CLK_INFRA_104M_SPI1>,
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+ <&infracfg CLK_INFRA_66M_SPI1_HCK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk",
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+ "hclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi2: spi@11009000 {
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+ compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm";
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+ reg = <0 0x11009000 0 0x100>;
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+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&topckgen CLK_TOP_MPLL_D2>,
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+ <&topckgen CLK_TOP_SPI_SEL>,
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+ <&infracfg CLK_INFRA_104M_SPI2_BCK>,
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+ <&infracfg CLK_INFRA_66M_SPI2_HCK>;
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+ clock-names = "parent-clk", "sel-clk", "spi-clk",
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+ "hclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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lvts: lvts@1100a000 {
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compatible = "mediatek,mt7988-lvts-ap";
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#thermal-sensor-cells = <1>;
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