forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
75 lines
2.0 KiB
Diff
75 lines
2.0 KiB
Diff
From 1861c63ba7bb7f8a5145d4ceabcf346f274da61f Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Tue, 22 Apr 2025 15:24:30 +0200
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Subject: [PATCH 28/32] arm64: dts: mediatek: mt7988: Add xsphy for
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ssusb0/pcie2
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First usb and third pcie controller on mt7988 need a xs-phy to work
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properly.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 36 +++++++++++++++++++++++
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1 file changed, 36 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -334,6 +334,8 @@
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<&infracfg CLK_INFRA_133M_USB_HCK>,
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<&infracfg CLK_INFRA_USB_XHCI>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
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+ phys = <&xphyu2port0 PHY_TYPE_USB2>,
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+ <&xphyu3port0 PHY_TYPE_USB3>;
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status = "disabled";
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};
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@@ -398,6 +400,9 @@
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pinctrl-0 = <&pcie2_pins>;
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status = "disabled";
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+ phys = <&xphyu3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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@@ -548,6 +553,37 @@
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};
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};
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+
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+ topmisc: system-controller@11d10084 {
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+ compatible = "mediatek,mt7988-topmisc",
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+ "syscon";
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+ reg = <0 0x11d10084 0 0xff80>;
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+ };
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+
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+ xs-phy@11e10000 {
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+ compatible = "mediatek,mt7988-xsphy",
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+ "mediatek,xsphy";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ xphyu2port0: usb-phy@11e10000 {
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+ reg = <0 0x11e10000 0 0x400>;
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+ clocks = <&infracfg CLK_INFRA_USB_UTMI>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ };
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+
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+ xphyu3port0: usb-phy@11e13000 {
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+ reg = <0 0x11e13400 0 0x500>;
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+ clocks = <&infracfg CLK_INFRA_USB_PIPE>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ mediatek,syscon-type = <&topmisc 0x194 0>;
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+ };
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+ };
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+
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clock-controller@11f40000 {
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compatible = "mediatek,mt7988-xfi-pll";
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reg = <0 0x11f40000 0 0x1000>;
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