forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
703 lines
19 KiB
Diff
703 lines
19 KiB
Diff
From 3986156b3ba97a9c280f4dfe0efbccf52e1fc488 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Wed, 28 Dec 2022 23:44:42 +0000
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Subject: [PATCH] complete mt7981 dts
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working:
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* Ethernet (fully working incl. ppe)
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* UART
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* SPI-NAND flash
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* thermal sensors (SoC and mxl-gpy)
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* random number generator via SMC
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* USB 1.1, 2.0 and 3.0
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* WiFi with MT7976C 2.4G+5G DBDC incl. WED offloading
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* PWM
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--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
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@@ -1,7 +1,14 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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#include <dt-bindings/clock/mediatek,mt7981-clk.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/mux/mux.h>
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+#include <dt-bindings/pinctrl/mt65xx.h>
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+#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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/ {
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@@ -41,6 +48,57 @@
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method = "smc";
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};
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+ fan: pwm-fan {
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+ compatible = "pwm-fan";
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+ /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
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+ cooling-levels = <0 128 192 255>;
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+ #cooling-cells = <2>;
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+ status = "disabled";
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ /* 64 KiB reserved for ramoops/pstore */
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+ ramoops@42ff0000 {
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+ compatible = "ramoops";
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+ reg = <0 0x42ff0000 0 0x10000>;
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+ record-size = <0x1000>;
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+ };
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+
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+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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+ secmon_reserved: secmon@43000000 {
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+ reg = <0 0x43000000 0 0x30000>;
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+ no-map;
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+ };
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+
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+ wmcpu_emi: wmcpu-reserved@47c80000 {
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+ reg = <0 0x47c80000 0 0x100000>;
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+ no-map;
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+ };
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+
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+ wo_emi0: wo-emi@47d80000 {
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+ reg = <0 0x47d80000 0 0x40000>;
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+ no-map;
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+ };
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+
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+ wo_data: wo-data@47dc0000 {
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+ reg = <0 0x47dc0000 0 0x240000>;
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+ no-map;
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+ };
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+ };
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+
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soc {
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compatible = "simple-bus";
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ranges;
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@@ -76,13 +134,13 @@
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#reset-cells = <1>;
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};
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- clock-controller@1001e000 {
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- compatible = "mediatek,mt7981-apmixedsys";
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+ apmixedsys: clock-controller@1001e000 {
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+ compatible = "mediatek,mt7981-apmixedsys", "syscon";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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- pwm@10048000 {
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+ pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_PWM_STA>,
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@@ -94,7 +152,21 @@
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#pwm-cells = <2>;
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};
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- serial@11002000 {
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+ crypto: crypto@10320000 {
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+ compatible = "inside-secure,safexcel-eip97";
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+ reg = <0 0x10320000 0 0x40000>;
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+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
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+ clocks = <&topckgen CLK_TOP_EIP97B>;
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+ clock-names = "top_eip97_ck";
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+ assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
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+ };
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+
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+ uart0: serial@11002000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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@@ -105,7 +177,7 @@
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status = "disabled";
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};
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- serial@11003000 {
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+ uart1: serial@11003000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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@@ -116,7 +188,7 @@
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status = "disabled";
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};
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- serial@11004000 {
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+ uart2: serial@11004000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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@@ -127,11 +199,12 @@
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status = "disabled";
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};
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- i2c@11007000 {
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+ i2c0: i2c@11007000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11007000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ clock-div = <1>;
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clocks = <&infracfg CLK_INFRA_I2C0_CK>,
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<&infracfg CLK_INFRA_AP_DMA_CK>,
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<&infracfg CLK_INFRA_I2C_MCK_CK>,
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@@ -142,7 +215,32 @@
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status = "disabled";
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};
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- spi@11009000 {
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+ thermal: thermal@1100c800 {
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+ #thermal-sensor-cells = <1>;
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+ compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
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+ reg = <0 0x1100c800 0 0x800>;
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+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_THERM_CK>,
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+ <&infracfg CLK_INFRA_ADC_26M_CK>;
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+ clock-names = "therm", "auxadc";
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+ mediatek,auxadc = <&auxadc>;
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+ mediatek,apmixedsys = <&apmixedsys>;
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+ nvmem-cells = <&thermal_calibration>;
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+ nvmem-cell-names = "calibration-data";
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+ };
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+
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+ auxadc: adc@1100d000 {
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+ compatible = "mediatek,mt7981-auxadc",
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+ "mediatek,mt7986-auxadc",
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+ "mediatek,mt7622-auxadc";
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+ reg = <0 0x1100d000 0 0x1000>;
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+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
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+ <&infracfg CLK_INFRA_ADC_FRC_CK>;
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+ clock-names = "main", "32k";
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+ #io-channel-cells = <1>;
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+ };
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+
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+ spi2: spi@11009000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x11009000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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@@ -156,7 +254,7 @@
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status = "disabled";
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};
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- spi@1100a000 {
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+ spi0: spi@1100a000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100a000 0 0x1000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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@@ -170,7 +268,7 @@
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status = "disabled";
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};
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- spi@1100b000 {
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+ spi1: spi@1100b000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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@@ -184,6 +282,41 @@
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status = "disabled";
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};
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+ pcie: pcie@11280000 {
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+ compatible = "mediatek,mt7981-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ reg = <0 0x11280000 0 0x4000>;
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+ reg-names = "pcie-mac";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000
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+ 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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+
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+ clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
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+ <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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+ <&infracfg CLK_INFRA_IPCIER_CK>,
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+ <&infracfg CLK_INFRA_IPCIEB_CK>;
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+
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+ phys = <&u3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
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+ <0 0 0 2 &pcie_intc 1>,
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+ <0 0 0 3 &pcie_intc 2>,
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+ <0 0 0 4 &pcie_intc 3>;
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+ pcie_intc: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ };
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+ };
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+
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pio: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0 0x11d00000 0 0x1000>,
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@@ -204,6 +337,49 @@
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gpio-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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+
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+ mdio_pins: mdc-mdio-pins {
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+ mux {
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+ function = "eth";
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+ groups = "smi_mdc_mdio";
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+ };
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+ };
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+
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+ uart0_pins: uart0-pins {
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+ mux {
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+ function = "uart";
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+ groups = "uart0";
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+ };
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+ };
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+
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+ wifi_dbdc_pins: wifi-dbdc-pins {
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+ mux {
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+ function = "eth";
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+ groups = "wf0_mode1";
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+ };
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+ conf {
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+ pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
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+ "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
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+ "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
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+ "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
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+ "WF_CBA_RESETB", "WF_DIG_RESETB";
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+ drive-strength = <4>;
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+ };
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+ };
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+
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+ gbe_led0_pins: gbe-led0-pins {
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+ mux {
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+ function = "led";
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+ groups = "gbe_led0";
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+ };
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+ };
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+
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+ gbe_led1_pins: gbe-led1-pins {
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+ mux {
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+ function = "led";
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+ groups = "gbe_led1";
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+ };
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+ };
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};
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efuse@11f20000 {
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@@ -211,17 +387,316 @@
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reg = <0 0x11f20000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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+
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+ thermal_calibration: thermal-calib@274 {
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+ reg = <0x274 0xc>;
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+ };
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+
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+ phy_calibration: phy-calib@8dc {
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+ reg = <0x8dc 0x10>;
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+ };
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+
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+ comb_rx_imp_p0: usb3-rx-imp@8c8 {
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+ reg = <0x8c8 1>;
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+ bits = <0 5>;
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+ };
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+
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+ comb_tx_imp_p0: usb3-tx-imp@8c8 {
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+ reg = <0x8c8 2>;
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+ bits = <5 5>;
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+ };
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+
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+ comb_intr_p0: usb3-intr@8c9 {
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+ reg = <0x8c9 1>;
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+ bits = <2 6>;
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+ };
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};
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- clock-controller@15000000 {
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+ ethsys: clock-controller@15000000 {
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compatible = "mediatek,mt7981-ethsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- wifi@18000000 {
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+ wed: wed@15010000 {
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+ compatible = "mediatek,mt7981-wed",
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+ "mediatek,mt7986-wed",
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+ "syscon";
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+ reg = <0 0x15010000 0 0x1000>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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+ memory-region = <&wo_emi0>, <&wo_data>;
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+ memory-region-names = "wo-emi", "wo-data";
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+ mediatek,wo-ccif = <&wo_ccif0>;
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+ mediatek,wo-ilm = <&wo_ilm0>;
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+ mediatek,wo-dlm = <&wo_dlm0>;
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+ mediatek,wo-cpuboot = <&wo_cpuboot>;
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+ };
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+
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+ eth: ethernet@15100000 {
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+ compatible = "mediatek,mt7981-eth";
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+ reg = <0 0x15100000 0 0x80000>;
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+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <ðsys CLK_ETH_FE_EN>,
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+ <ðsys CLK_ETH_GP2_EN>,
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+ <ðsys CLK_ETH_GP1_EN>,
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+ <ðsys CLK_ETH_WOCPU0_EN>,
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+ <&sgmiisys0 CLK_SGM0_TX_EN>,
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+ <&sgmiisys0 CLK_SGM0_RX_EN>,
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+ <&sgmiisys0 CLK_SGM0_CK0_EN>,
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+ <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
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+ <&sgmiisys1 CLK_SGM1_TX_EN>,
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+ <&sgmiisys1 CLK_SGM1_RX_EN>,
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+ <&sgmiisys1 CLK_SGM1_CK1_EN>,
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+ <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
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+ <&topckgen CLK_TOP_SGM_REG>,
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+ <&topckgen CLK_TOP_NETSYS_SEL>,
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+ <&topckgen CLK_TOP_NETSYS_500M_SEL>;
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+ clock-names = "fe", "gp2", "gp1", "wocpu0",
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+ "sgmii_tx250m", "sgmii_rx250m",
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+ "sgmii_cdr_ref", "sgmii_cdr_fb",
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+ "sgmii2_tx250m", "sgmii2_rx250m",
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+ "sgmii2_cdr_ref", "sgmii2_cdr_fb",
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+ "sgmii_ck", "netsys0", "netsys1";
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+ assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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+ <&topckgen CLK_TOP_SGM_325M_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
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+ <&topckgen CLK_TOP_CB_SGM_325M>;
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+ mediatek,ethsys = <ðsys>;
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+ mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
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+ mediatek,infracfg = <&topmisc>;
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+ mediatek,wed = <&wed>;
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+ status = "disabled";
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+
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+ mdio_bus: mdio-bus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ int_gbe_phy: ethernet-phy@0 {
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+ reg = <0>;
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ phy-mode = "gmii";
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+ phy-is-integrated;
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+ nvmem-cells = <&phy_calibration>;
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+ nvmem-cell-names = "phy-cal-data";
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+
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+ leds {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ int_gbe_phy_led0: int-gbe-phy-led0@0 {
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+ reg = <0>;
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+ function = LED_FUNCTION_LAN;
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+ pinctrl-0 = <&gbe_led0_pins>;
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+ pinctrl-names = "default";
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+ status = "disabled";
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+ };
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+
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+ int_gbe_phy_led1: int-gbe-phy-led1@1 {
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+ reg = <1>;
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+ function = LED_FUNCTION_LAN;
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+ pinctrl-0 = <&gbe_led1_pins>;
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+ pinctrl-names = "default";
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+ status = "disabled";
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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+ wdma: wdma@15104800 {
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+ compatible = "mediatek,wed-wdma";
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+ reg = <0 0x15104800 0 0x400>,
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+ <0 0x15104c00 0 0x400>;
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+ };
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+
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+ ap2woccif: ap2woccif@151a5000 {
|
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+ compatible = "mediatek,ap2woccif";
|
|
+ reg = <0 0x151a5000 0 0x1000>,
|
|
+ <0 0x151ad000 0 0x1000>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ wo_dlm0: syscon@151e8000 {
|
|
+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
|
+ reg = <0 0x151e8000 0 0x2000>;
|
|
+ };
|
|
+
|
|
+ wo_ilm0: syscon@151e0000 {
|
|
+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
|
+ reg = <0 0x151e0000 0 0x8000>;
|
|
+ };
|
|
+
|
|
+ wo_cpuboot: syscon@15194000 {
|
|
+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
|
+ reg = <0 0x15194000 0 0x1000>;
|
|
+ };
|
|
+
|
|
+ wo_ccif0: syscon@151a5000 {
|
|
+ compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
|
+ reg = <0 0x151a5000 0 0x1000>;
|
|
+ interrupt-parent = <&gic>;
|
|
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ };
|
|
+
|
|
+ sgmiisys0: syscon@10060000 {
|
|
+ compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
|
|
+ reg = <0 0x10060000 0 0x1000>;
|
|
+ mediatek,pnswap;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ sgmiisys1: syscon@10070000 {
|
|
+ compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
|
|
+ reg = <0 0x10070000 0 0x1000>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ topmisc: topmisc@11d10000 {
|
|
+ compatible = "mediatek,mt7981-topmisc", "syscon";
|
|
+ reg = <0 0x11d10000 0 0x10000>;
|
|
+ #clock-cells = <1>;
|
|
+ };
|
|
+
|
|
+ snand: snfi@11005000 {
|
|
+ compatible = "mediatek,mt7986-snand";
|
|
+ reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
|
|
+ reg-names = "nfi", "ecc";
|
|
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
|
|
+ <&infracfg CLK_INFRA_NFI1_CK>,
|
|
+ <&infracfg CLK_INFRA_NFI_HCK_CK>;
|
|
+ clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
|
+ assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
|
+ <&topckgen CLK_TOP_NFI1X_SEL>;
|
|
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
|
|
+ <&topckgen CLK_TOP_CB_M_D8>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mmc0: mmc@11230000 {
|
|
+ compatible = "mediatek,mt7986-mmc",
|
|
+ "mediatek,mt7981-mmc";
|
|
+ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_MSDC_CK>,
|
|
+ <&infracfg CLK_INFRA_MSDC_HCK_CK>,
|
|
+ <&infracfg CLK_INFRA_MSDC_66M_CK>,
|
|
+ <&infracfg CLK_INFRA_MSDC_133M_CK>;
|
|
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
|
|
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
|
|
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
|
+ <&topckgen CLK_TOP_CB_NET2_D2>;
|
|
+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ wed_pcie: wed_pcie@10003000 {
|
|
+ compatible = "mediatek,wed_pcie";
|
|
+ reg = <0 0x10003000 0 0x10>;
|
|
+ };
|
|
+
|
|
+ consys: consys@10000000 {
|
|
+ compatible = "mediatek,mt7981-consys";
|
|
+ reg = <0 0x10000000 0 0x8600000>;
|
|
+ memory-region = <&wmcpu_emi>;
|
|
+ };
|
|
+
|
|
+ xhci: usb@11200000 {
|
|
+ compatible = "mediatek,mt7986-xhci",
|
|
+ "mediatek,mtk-xhci";
|
|
+ reg = <0 0x11200000 0 0x2e00>,
|
|
+ <0 0x11203e00 0 0x0100>;
|
|
+ reg-names = "mac", "ippc";
|
|
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
|
|
+ <&infracfg CLK_INFRA_IUSB_CK>,
|
|
+ <&infracfg CLK_INFRA_IUSB_133_CK>,
|
|
+ <&infracfg CLK_INFRA_IUSB_66M_CK>,
|
|
+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
|
|
+ clock-names = "sys_ck",
|
|
+ "ref_ck",
|
|
+ "mcu_ck",
|
|
+ "dma_ck",
|
|
+ "xhci_ck";
|
|
+ phys = <&u2port0 PHY_TYPE_USB2>,
|
|
+ <&u3port0 PHY_TYPE_USB3>;
|
|
+ vusb33-supply = <®_3p3v>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb_phy: usb-phy@11e10000 {
|
|
+ compatible = "mediatek,mt7981",
|
|
+ "mediatek,generic-tphy-v2";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ ranges = <0 0 0x11e10000 0x1700>;
|
|
+ status = "disabled";
|
|
+
|
|
+ u2port0: usb-phy@0 {
|
|
+ reg = <0x0 0x700>;
|
|
+ clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <1>;
|
|
+ };
|
|
+
|
|
+ u3port0: usb-phy@700 {
|
|
+ reg = <0x700 0x900>;
|
|
+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <1>;
|
|
+ mediatek,syscon-type = <&topmisc 0x218 0>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
+ afe: audio-controller@11210000 {
|
|
+ compatible = "mediatek,mt79xx-audio";
|
|
+ reg = <0 0x11210000 0 0x9000>;
|
|
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_26M_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_L_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
|
|
+ <&infracfg CLK_INFRA_AUD_EG2_CK>,
|
|
+ <&topckgen CLK_TOP_AUD_SEL>;
|
|
+ clock-names = "aud_bus_ck",
|
|
+ "aud_26m_ck",
|
|
+ "aud_l_ck",
|
|
+ "aud_aud_ck",
|
|
+ "aud_eg2_ck",
|
|
+ "aud_sel";
|
|
+ assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
|
+ <&topckgen CLK_TOP_A1SYS_SEL>,
|
|
+ <&topckgen CLK_TOP_AUD_L_SEL>,
|
|
+ <&topckgen CLK_TOP_A_TUNER_SEL>;
|
|
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
|
|
+ <&topckgen CLK_TOP_APLL2_D4>,
|
|
+ <&topckgen CLK_TOP_CB_APLL2_196M>,
|
|
+ <&topckgen CLK_TOP_APLL2_D4>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ ice: ice_debug {
|
|
+ compatible = "mediatek,mt7981-ice_debug",
|
|
+ "mediatek,mt2701-ice_debug";
|
|
+ clocks = <&infracfg CLK_INFRA_DBG_CK>;
|
|
+ clock-names = "ice_dbg";
|
|
+ };
|
|
+
|
|
+ wifi: wifi@18000000 {
|
|
compatible = "mediatek,mt7981-wmac";
|
|
+ pinctrl-0 = <&wifi_dbdc_pins>;
|
|
+ pinctrl-names = "dbdc";
|
|
reg = <0 0x18000000 0 0x1000000>,
|
|
<0 0x10003000 0 0x1000>,
|
|
<0 0x11d10000 0 0x1000>;
|
|
@@ -234,6 +709,67 @@
|
|
clock-names = "mcu", "ap2conn";
|
|
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
|
reset-names = "consys";
|
|
+ memory-region = <&wmcpu_emi>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ thermal-zones {
|
|
+ cpu_thermal: cpu-thermal {
|
|
+ polling-delay-passive = <1000>;
|
|
+ polling-delay = <1000>;
|
|
+ thermal-sensors = <&thermal 0>;
|
|
+ trips {
|
|
+ cpu_trip_crit: crit {
|
|
+ temperature = <125000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+
|
|
+ cpu_trip_hot: hot {
|
|
+ temperature = <120000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "hot";
|
|
+ };
|
|
+
|
|
+ cpu_trip_active_high: active-high {
|
|
+ temperature = <115000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "active";
|
|
+ };
|
|
+
|
|
+ cpu_trip_active_med: active-med {
|
|
+ temperature = <85000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "active";
|
|
+ };
|
|
+
|
|
+ cpu_trip_active_low: active-low {
|
|
+ temperature = <60000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "active";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ cpu-active-high {
|
|
+ /* active: set fan to cooling level 3 */
|
|
+ cooling-device = <&fan 3 3>;
|
|
+ trip = <&cpu_trip_active_high>;
|
|
+ };
|
|
+
|
|
+ cpu-active-med {
|
|
+ /* active: set fan to cooling level 2 */
|
|
+ cooling-device = <&fan 2 2>;
|
|
+ trip = <&cpu_trip_active_med>;
|
|
+ };
|
|
+
|
|
+ cpu-active-low {
|
|
+ /* passive: set fan to cooling level 1 */
|
|
+ cooling-device = <&fan 1 1>;
|
|
+ trip = <&cpu_trip_active_low>;
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|
|
|
|
@@ -245,4 +781,8 @@
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
+
|
|
+ trng {
|
|
+ compatible = "mediatek,mt7981-rng";
|
|
+ };
|
|
};
|