forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
85 lines
2.3 KiB
Diff
85 lines
2.3 KiB
Diff
From b10331c8faa1208c61fb98d9b65da2828e239113 Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Tue, 17 Dec 2024 10:12:21 +0100
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Subject: [PATCH 09/32] arm64: dts: mediatek: mt7988: Add CPU OPP table for
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clock scaling
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Add operating points defining frequency/voltages of cpu cores.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -21,6 +21,10 @@
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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+ <&topckgen CLK_TOP_XTAL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cluster0_opp>;
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};
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cpu@1 {
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@@ -28,6 +32,10 @@
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reg = <0x1>;
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device_type = "cpu";
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enable-method = "psci";
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+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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+ <&topckgen CLK_TOP_XTAL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cluster0_opp>;
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};
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cpu@2 {
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@@ -35,6 +43,10 @@
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reg = <0x2>;
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device_type = "cpu";
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enable-method = "psci";
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+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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+ <&topckgen CLK_TOP_XTAL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cluster0_opp>;
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};
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cpu@3 {
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@@ -42,6 +54,32 @@
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reg = <0x3>;
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device_type = "cpu";
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enable-method = "psci";
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+ clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
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+ <&topckgen CLK_TOP_XTAL>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cluster0_opp>;
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+ };
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+
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+ cluster0_opp: opp-table-0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <850000>;
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+ };
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+ opp-1100000000 {
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+ opp-hz = /bits/ 64 <1100000000>;
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+ opp-microvolt = <850000>;
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+ };
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+ opp-1500000000 {
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+ opp-hz = /bits/ 64 <1500000000>;
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+ opp-microvolt = <850000>;
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+ };
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <900000>;
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+ };
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};
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};
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