forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
53 lines
1.9 KiB
Diff
53 lines
1.9 KiB
Diff
From de6ba1a3ef621762394e841888de3e0ed127e20a Mon Sep 17 00:00:00 2001
|
|
From: Frank Wunderlich <frank-w@public-files.de>
|
|
Date: Tue, 17 Dec 2024 10:12:16 +0100
|
|
Subject: [PATCH 05/32] arm64: dts: mediatek: mt7988: Add mmc support
|
|
|
|
Add devicetree node for MMC controller.
|
|
|
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de
|
|
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
---
|
|
arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++-
|
|
1 file changed, 20 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
|
|
@@ -112,7 +112,7 @@
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
- clock-controller@1001e000 {
|
|
+ apmixedsys: clock-controller@1001e000 {
|
|
compatible = "mediatek,mt7988-apmixedsys";
|
|
reg = <0 0x1001e000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
@@ -293,6 +293,25 @@
|
|
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
|
|
};
|
|
|
|
+ mmc0: mmc@11230000 {
|
|
+ compatible = "mediatek,mt7988-mmc";
|
|
+ reg = <0 0x11230000 0 0x1000>,
|
|
+ <0 0x11D60000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ clocks = <&infracfg CLK_INFRA_MSDC400>,
|
|
+ <&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
+ <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
|
|
+ <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
|
|
+ assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
|
|
+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
|
|
+ assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
|
|
+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
|
|
+ clock-names = "source", "hclk", "axi_cg", "ahb_cg";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
clock-controller@11f40000 {
|
|
compatible = "mediatek,mt7988-xfi-pll";
|
|
reg = <0 0x11f40000 0 0x1000>;
|