forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
86 lines
2.4 KiB
Diff
86 lines
2.4 KiB
Diff
From a01cc71a8c55e7fc12cb37109953ad9c58a12d4f Mon Sep 17 00:00:00 2001
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From: Frank Wunderlich <frank-w@public-files.de>
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Date: Tue, 17 Dec 2024 09:54:29 +0100
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Subject: [PATCH 03/32] arm64: dts: mediatek: mt7988: Add pinctrl support
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Add mt7988a pinctrl node.
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Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -3,6 +3,7 @@
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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+#include <dt-bindings/pinctrl/mt65xx.h>
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/ {
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compatible = "mediatek,mt7988a";
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@@ -105,6 +106,59 @@
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#clock-cells = <1>;
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};
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+ pio: pinctrl@1001f000 {
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+ compatible = "mediatek,mt7988-pinctrl";
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+ reg = <0 0x1001f000 0 0x1000>,
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+ <0 0x11c10000 0 0x1000>,
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+ <0 0x11d00000 0 0x1000>,
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+ <0 0x11d20000 0 0x1000>,
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+ <0 0x11e00000 0 0x1000>,
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+ <0 0x11f00000 0 0x1000>,
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+ <0 0x1000b000 0 0x1000>;
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+ reg-names = "gpio", "iocfg_tr",
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+ "iocfg_br", "iocfg_rb",
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+ "iocfg_lb", "iocfg_tl", "eint";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ gpio-ranges = <&pio 0 0 84>;
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+ interrupt-controller;
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+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-parent = <&gic>;
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+ #interrupt-cells = <2>;
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+
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+ pcie0_pins: pcie0-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
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+ "pcie_wake_n0_0";
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+ };
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+ };
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+
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+ pcie1_pins: pcie1-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
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+ "pcie_wake_n1_0";
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+ };
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+ };
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+
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+ pcie2_pins: pcie2-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
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+ "pcie_wake_n2_0";
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+ };
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+ };
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+
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+ pcie3_pins: pcie3-pins {
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+ mux {
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+ function = "pcie";
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+ groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
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+ "pcie_wake_n3_0";
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+ };
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+ };
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+ };
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+
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pwm@10048000 {
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compatible = "mediatek,mt7988-pwm";
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reg = <0 0x10048000 0 0x1000>;
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