forked from Openwrt-EcoNet/openwrt
f9206d1111
Replace downstream files by patches, either backports of those which have already applied or pending patches tracked on patchwork. This is done to make future maintainance more easy. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
72 lines
2.4 KiB
Diff
72 lines
2.4 KiB
Diff
From 52e2ca3be4b6d451fef0a2cd337157dd021b830f Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Wed, 5 Jun 2024 10:54:33 +0200
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Subject: [PATCH 01/32] arm64: dts: mediatek: mt7988: add UART controllers
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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MT7988 has three on-SoC UART controllers that support M16C450 and
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M16550A modes.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/20240605085433.26513-2-zajec5@gmail.com
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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---
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arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 35 ++++++++++++++++++++++-
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1 file changed, 34 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
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@@ -86,7 +86,7 @@
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#clock-cells = <1>;
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};
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- clock-controller@1001b000 {
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+ topckgen: clock-controller@1001b000 {
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compatible = "mediatek,mt7988-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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@@ -124,6 +124,39 @@
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status = "disabled";
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};
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+ serial@11000000 {
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+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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+ reg = <0 0x11000000 0 0x100>;
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "uart", "wakeup";
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&infracfg CLK_INFRA_52M_UART0_CK>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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+ serial@11000100 {
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+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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+ reg = <0 0x11000100 0 0x100>;
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+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "uart", "wakeup";
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&infracfg CLK_INFRA_52M_UART1_CK>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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+ serial@11000200 {
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+ compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart";
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+ reg = <0 0x11000200 0 0x100>;
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+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "uart", "wakeup";
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+ clocks = <&topckgen CLK_TOP_UART_SEL>,
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+ <&infracfg CLK_INFRA_52M_UART2_CK>;
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+ clock-names = "baud", "bus";
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+ status = "disabled";
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+ };
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+
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i2c@11003000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11003000 0 0x1000>,
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