openwrt_mitrastar/target/linux/mediatek/dts/mt7981b-glinet-gl-mt2500.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/dts-v1/;
#include "mt7981b.dtsi"

/ {
	model = "GL.iNet GL-MT2500";
	compatible = "glinet,gl-mt2500", "mediatek,mt7981";

	aliases {
		label-mac-device = &gmac0;
		led-boot = &led_sys_white;
		led-failsafe = &led_sys_blue;
		led-running = &led_sys_white;
		led-upgrade = &led_sys_blue;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs-append = " root=PARTLABEL=rootfs rootwait";
	};

	gpio-keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-vpn {
			label = "white:vpn";
			gpios = <&pio 31 GPIO_ACTIVE_LOW>;
		};

		led_sys_white: led-system-white {
			label = "white:system";
			gpios = <&pio 30 GPIO_ACTIVE_LOW>;
		};

		led_sys_blue: led-system-blue {
			label = "blue:system";
			gpios = <&pio 29 GPIO_ACTIVE_LOW>;
		};
	};

	usb_vbus: regulstor-usb {
		compatible = "regulator-fixed";

		regulator-name = "usb-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;

		gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-boot-on;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&pio {
	mmc0_pins_default: mmc0-pins-default {
		mux {
			function = "flash";
			groups = "emmc_45";
		};
		conf-cmd-dat {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
				"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
			input-enable;
			drive-strength = <MTK_DRIVE_12mA>;
			mediatek,pull-up-adv = <1>;
		};
		conf-clk {
			pins = "SPI1_CS";
			drive-strength = <MTK_DRIVE_12mA>;
			mediatek,pull-down-adv = <2>;
		};
	};
	mmc0_pins_uhs: mmc0-pins-uhs {
		mux {
			function = "flash";
			groups = "emmc_45";
		};
		conf-cmd-dat {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
				"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
				"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
			input-enable;
			drive-strength = <MTK_DRIVE_12mA>;
			mediatek,pull-up-adv = <1>;
		};
		conf-clk {
			pins = "SPI1_CS";
			drive-strength = <MTK_DRIVE_12mA>;
			mediatek,pull-down-adv = <2>;
		};
	};
};

&uart0 {
	status = "okay";
};

&watchdog {
	status = "okay";
};

&eth {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		nvmem-cells = <&macaddr_boot1_a 0>;
		nvmem-cell-names = "mac-address";
		reg = <0>;

		phy-mode = "2500base-x";
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		nvmem-cells = <&macaddr_boot1_a 1>;
		nvmem-cell-names = "mac-address";
		reg = <1>;
		phy-mode = "gmii";
		phy-handle = <&int_gbe_phy>;
	};
};

&mdio_bus {
	reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
	reset-delay-us = <600>;
	reset-post-delay-us = <20000>;
};

&usb_phy {
	status = "okay";
};

&xhci {
	status = "okay";
	vbus-supply = <&usb_vbus>;
};

&mmc0 {
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <8>;
	max-frequency = <26000000>;
	vmmc-supply = <&reg_3p3v>;
	cap-mmc-highspeed;
	non-removable;

	card@0 {
		compatible = "mmc-card";
		reg = <0>;

		block {
			compatible = "block-device";

			partitions {
				block-partition-u-boot-env {
					partname = "u-boot-env";

					nvmem-layout {
						compatible = "u-boot,env";
					};
				};
			};
		};

		boot1 {
			compatible = "block-device";

			nvmem-layout {
				compatible = "fixed-layout";
				#address-cells = <1>;
				#size-cells = <1>;

				macaddr_boot1_a: macaddr@a {
					compatible = "mac-base";
					reg = <0xa 0x6>;
					#nvmem-cell-cells = <1>;
				};

				ddns@10 {
					reg = <0x10 0x10>;
				};

				sn-bak@20 {
					reg = <0x20 0x10>;
				};

				sn@30 {
					reg = <0x30 0x10>;
				};

				country-code@88 {
					reg = <0x88 0x10>;
				};
			};
		};
	};
};