openwrt_mitrastar/target/linux/mediatek/dts/mt7981b-cudy-ap3000-v1.dts

// SPDX-License-Identifier: GPL-2.0-only OR MIT

/dts-v1/;

#include "mt7981b.dtsi"

/ {
	model = "Cudy AP3000 v1";
	compatible = "cudy,ap3000-v1", "mediatek,mt7981";

	aliases {
		label-mac-device = &gmac0;
		led-boot = &status_led;
		led-failsafe = &status_led;
		led-running = &status_led;
		led-upgrade = &status_led;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		led-0 {
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_WLAN_2GHZ;
			gpios = <&pio 4 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy0tpt";
		};

		led-1 {
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_WLAN_5GHZ;
			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy1tpt";
		};

		status_led: led-2 {
			color = <LED_COLOR_ID_AMBER>;
			function = LED_FUNCTION_STATUS;
			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
		};
	};

	watchdog {
		compatible = "linux,wdt-gpio";
		gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
		hw_algo = "level";
		hw_margin_ms = <10000>;
		always-running;
	};
};

&uart0 {
	status = "okay";
};

&watchdog {
	status = "okay";
};

&eth {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-handle = <&phy1>;
		phy-mode = "2500base-x";

		nvmem-cell-names = "mac-address";
		nvmem-cells = <&macaddr_bdinfo_de00 0>;
	};
};

&mdio_bus {
	phy1: phy@1 {
		reg = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
		reset-assert-us = <100000>;
		reset-deassert-us = <100000>;
	};
};

&pio {
	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};

		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
		};

		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	/* ESMT F50L2G41XA (256M) */
	spi_nand@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-nand";
		reg = <0>;

		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;

		spi-cal-enable;
		spi-cal-mode = "read-data";
		spi-cal-datalen = <7>;
		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>;
		spi-cal-addrlen = <5>;
		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;

		mediatek,nmbm;
		mediatek,bmt-max-ratio = <1>;
		mediatek,bmt-max-reserved-blocks = <64>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x0 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x100000 0x80000>;
			};

			partition@180000 {
				label = "factory";
				reg = <0x180000 0x200000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x1000>;
					};
				};
			};

			partition@380000 {
				label = "bdinfo";
				reg = <0x380000 0x40000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_bdinfo_de00: macaddr@de00 {
						compatible = "mac-base";
						reg = <0xde00 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@3C0000 {
				label = "fip";
				reg = <0x3C0000 0x200000>;
				read-only;
			};

			partition@5C0000 {
				label = "ubi";
				reg = <0x5C0000 0x4000000>;
			};
		};
	};
};

&wifi {
	nvmem-cell-names = "eeprom";
	nvmem-cells = <&eeprom_factory_0>;
	status = "okay";
};