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new-platform-econet-jun4
openwrt_mitrastar/package/kernel/mac80211/patches/rtl/085-v6.15-wifi-rtw88-Add-some-definitions-for-RTL8814AU.patch
Marty Jones 4a1aca5376 mac80211: realtek: rtw88: sync with v6.16 
Renamed 046..051 pending patches with the merged tag/hash.
Two patches were skipped, they make use of WQ_BH present since v6.14:
  13221be720
  3e3aa566dd
Manually refreshed 062-v6.14-wifi-rtw88-Add-support-for-LED-blinking.patch
Manually refreshed  063-v6.14-wifi-rtw88-add-RTW88_LEDS-depends-on-LEDS_CLASS-to-K.patch
Manually backported 090-v6.15-wifi-rtw88-Enable-the-new-RTL8814AE-RTL8814AU-driver.patch

git log --no-merges --pretty=oneline --abbrev-commit 4c2c372de...0daa521a drivers/net/wireless/realtek/rtw88:
4c2c372de2e1 wifi: rtw88: fix the 'para' buffer size to avoid reading out of bounds
f24d0d8c3cd7 wifi: rtw88: Fix the random "error beacon valid" messages for USB
80fe0bc1659c wifi: rtw88: usb: Upload the firmware in bigger chunks
490340faddea wifi: rtw88: usb: Reduce control message timeout to 500 ms
b7f0cc647e52 wifi: rtw88: rtw8822bu VID/PID for BUFFALO WI-U2-866DM
2c17afde9ff6 wifi: rtw88: Handle RTL8723D(S) with blank efuse
0ffa1ba81b35 wifi: rtw88: Fix RX aggregation settings for RTL8723DS
20d3c19bd8f9 wifi: rtw88: do not ignore hardware read error during DPK
fc5f5a0ec463 wifi: rtw88: sdio: call rtw_sdio_indicate_tx_status unconditionally
b2effcdc2379 wifi: rtw88: sdio: map mgmt frames to queue TX_DESC_QSEL_MGMT
581cf3a9cb61 wifi: rtw88: Fix the module names printed in dmesg
b8d49bb8d16a wifi: rtw88: Don't set SUPPORTS_AMSDU_IN_AMPDU for RTL8814AU
0d2a88690e58 wifi: rtw88: Set AMPDU factor to hardware for RTL8814A
dcbb7bb3a364 wifi: rtw88: usb: Enable RX aggregation for RTL8814AU
bf1103654df9 wifi: rtw88: usb: Enable switching the RTL8814AU to USB 3
625fbc16524a wifi: rtw88: usb: Remove redundant 'flush_workqueue()' calls
5c4cf36c538b wifi: rtw88: sdio: Remove redundant 'flush_workqueue()' calls
d58ad77d5cc2 wifi: rtw88: Add __nonstring annotations for unterminated strings
deb3ddeb1865 wifi: rtw88: Enable the new RTL8814AE/RTL8814AU drivers
bad060e8a425 wifi: rtw88: Add rtw8814au.c
dad8e8793102 wifi: rtw88: Add rtw8814ae.c
1a7545784642 wifi: rtw88: Add rtw8814a.{c,h}
e38246889cc9 wifi: rtw88: Add rtw8814a_table.c (part 2/2)
f4debfcb1b3c wifi: rtw88: Add rtw8814a_table.c (part 1/2)
679ec431477c wifi: rtw88: Add some definitions for RTL8814AU
c374281f8285 wifi: rtw88: Extend rtw_debugfs_get_tx_pwr_tbl() for RTL8814AU
cfebabdd351e wifi: rtw88: Extend rtw_debugfs_get_phy_info() for RTL8814AU
8b42c46cf665 wifi: rtw88: Extend rtw_phy_config_swing_table() for RTL8814AU
053a7aace020 wifi: rtw88: Fix rtw_rx_phy_stat() for RTL8814AU
6be7544d19fc wifi: rtw88: Fix rtw_init_vht_cap() for RTL8814AU
c7eea1ba05ca wifi: rtw88: Fix rtw_init_ht_cap() for RTL8814AU
86d04f8f991a wifi: rtw88: Fix rtw_desc_to_mcsrate() to handle MCS16-31
e66bca16638e wifi: rtw88: Fix rtw_mac_power_switch() for RTL8814AU
80c4668d024f wifi: rtw88: Add support for Mercusys MA30N and D-Link DWA-T185 rev. A1
9f00e2218e15 wifi: rtw88: Fix rtw_update_sta_info() for RTL8814AU
0f98a5959657 wifi: rtw88: Extend TX power stuff for 3-4 spatial streams
ad815f392003 wifi: rtw88: Rename RTW_RATE_SECTION_MAX to RTW_RATE_SECTION_NUM
e66f3b5c7535 wifi: rtw88: Constify some more structs and arrays
8f0076726b66 wifi: rtw88: Extend rtw_fw_send_ra_info() for RTL8814AU
d80e7d9b6ba3 wifi: rtw88: Extend rf_base_addr and rf_sipi_addr for RTL8814AU
62f726848da4 wifi: rtw88: Extend struct rtw_pwr_track_tbl for RTL8814AU
9e8243025cc0 wifi: rtw88: Fix download_firmware_validate() for RTL8814AU
8425f5c8f04d wifi: rtw88: Fix __rtw_download_firmware() for RTL8814AU
105dc94233e4 wifi: rtw88: Fix a typo of debug message in rtw8723d_iqk_check_tx_failed()
0d1d165eff9d wifi: rtw88: Don't use static local variable in rtw8821c_set_tx_power_index_by_rate
00451eb3bec7 wifi: rtw88: Don't use static local variable in rtw8822b_set_tx_power_index_by_rate
b4bfbc50b1b9 wifi: rtw88: add RTW88_LEDS depends on LEDS_CLASS to Kconfig
4b6652bc6d8d wifi: rtw88: Add support for LED blinking
fb2fcfbe5eef wifi: rtw88: sdio: Fix disconnection after beacon loss
a806a8160a0f wifi: rtw88: 8703b: Fix RX/TX issues
5ad483955acc wifi: rtw88: Delete rf_type member of struct rtw_sta_info
5b1b9545262b wifi: rtw88: Add USB PHY configuration
not backported (3e3aa566dd18 wifi: rtw88: usb: Preallocate and reuse the RX skbs)
not backported (13221be72034 wifi: rtw88: Handle C2H_ADAPTIVITY in rtw_fw_c2h_cmd_handle() )
e9048e2935f7 wifi: rtw88: usb: Copy instead of cloning the RX skb
74a72c367573 wifi: rtw88: 8821a/8812a: Set ptct_efuse_size to 0
59ab27a9f20f wifi: rtw88: 8812a: Support RFE type 2

Signed-off-by: Marty Jones <mj8263788@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/19052
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2025-06-08 16:10:40 +02:00

201 lines
5.8 KiB
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From 679ec431477cdb68d1cab068c008da0de7f842ef Mon Sep 17 00:00:00 2001
From: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Date: Fri, 7 Mar 2025 02:22:17 +0200
Subject: [PATCH] wifi: rtw88: Add some definitions for RTL8814AU
Add various register definitions which will be used by the new driver.
Signed-off-by: Bitterblue Smith <rtl8821cerfe2@gmail.com>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/1dcb5abb-26f8-4db5-be36-057de56465e5@gmail.com
---
drivers/net/wireless/realtek/rtw88/reg.h | 66 ++++++++++++++++++++++--
1 file changed, 62 insertions(+), 4 deletions(-)
--- a/drivers/net/wireless/realtek/rtw88/reg.h
+++ b/drivers/net/wireless/realtek/rtw88/reg.h
@@ -8,6 +8,7 @@
#define REG_SYS_FUNC_EN 0x0002
#define BIT_FEN_EN_25_1 BIT(13)
#define BIT_FEN_ELDR BIT(12)
+#define BIT_FEN_PCIEA BIT(6)
#define BIT_FEN_CPUEN BIT(2)
#define BIT_FEN_USBA BIT(2)
#define BIT_FEN_BB_GLB_RST BIT(1)
@@ -39,6 +40,9 @@
#define BIT_RF_RSTB BIT(1)
#define BIT_RF_EN BIT(0)
+#define REG_RF_CTRL1 0x0020
+#define REG_RF_CTRL2 0x0021
+
#define REG_AFE_CTRL1 0x0024
#define BIT_MAC_CLK_SEL (BIT(20) | BIT(21))
#define REG_EFUSE_CTRL 0x0030
@@ -73,6 +77,8 @@
#define BIT_BT_PTA_EN BIT(5)
#define BIT_WLRFE_4_5_EN BIT(2)
+#define REG_GPIO_PIN_CTRL 0x0044
+
#define REG_LED_CFG 0x004C
#define BIT_LNAON_SEL_EN BIT(26)
#define BIT_PAPE_SEL_EN BIT(25)
@@ -110,6 +116,7 @@
#define BIT_SDIO_PAD_E5 BIT(18)
#define REG_RF_B_CTRL 0x76
+#define REG_RF_CTRL3 0x0076
#define REG_AFE_CTRL_4 0x0078
#define BIT_CK320M_AFE_EN BIT(4)
@@ -603,15 +610,25 @@
#define REG_CCA2ND 0x0838
#define REG_L1PKTH 0x0848
#define REG_CLKTRK 0x0860
+#define REG_CSI_MASK_SETTING1 0x0874
+#define REG_NBI_SETTING 0x087c
+#define BIT_NBI_ENABLE BIT(13)
+#define REG_CSI_FIX_MASK0 0x0880
+#define REG_CSI_FIX_MASK1 0x0884
+#define REG_CSI_FIX_MASK6 0x0898
+#define REG_CSI_FIX_MASK7 0x089c
#define REG_ADCCLK 0x08AC
#define REG_HSSI_READ 0x08B0
#define REG_FPGA0_XCD_RF_PARA 0x08B4
#define REG_RX_MCS_LIMIT 0x08BC
#define REG_ADC160 0x08C4
+#define REG_DBGSEL 0x08fc
#define REG_ANTSEL_SW 0x0900
#define REG_DAC_RSTB 0x090c
+#define REG_PSD 0x0910
+#define BIT_PSD_INI GENMASK(23, 22)
#define REG_SINGLE_TONE_CONT_TX 0x0914
-
+#define REG_AGC_TABLE 0x0958
#define REG_RFE_CTRL_E 0x0974
#define REG_2ND_CCA_CTRL 0x0976
#define REG_IQK_COM00 0x0978
@@ -621,10 +638,18 @@
#define REG_FAS 0x09a4
#define REG_RXSB 0x0a00
+#define BIT_RXSB_ANA_DIV BIT(15)
#define REG_CCK_RX 0x0a04
#define REG_CCK_PD_TH 0x0a0a
-
-#define REG_CCK0_FAREPORT 0xa2c
+#define REG_PRECTRL 0x0a14
+#define BIT_DIS_CO_PATHSEL BIT(7)
+#define BIT_IQ_WGT GENMASK(9, 8)
+#define REG_CCA_MF 0x0a20
+#define BIT_MBC_WIN GENMASK(5, 4)
+#define REG_CCK0_TX_FILTER1 0x0a20
+#define REG_CCK0_TX_FILTER2 0x0a24
+#define REG_CCK0_DEBUG_PORT 0x0a28
+#define REG_CCK0_FAREPORT 0x0a2c
#define BIT_CCK0_2RX BIT(18)
#define BIT_CCK0_MRC BIT(22)
#define REG_FA_CCK 0x0a5c
@@ -643,10 +668,18 @@
#define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)
#define DIS_DPD_RATEALL GENMASK(9, 0)
+#define REG_CCA 0x0a70
+#define BIT_CCA_CO BIT(7)
+#define REG_ANTSEL 0x0a74
+#define BIT_ANT_BYCO BIT(8)
+#define REG_CCKTX 0x0a84
+#define BIT_CMB_CCA_2R BIT(28)
+
#define REG_CNTRST 0x0b58
#define REG_3WIRE_SWA 0x0c00
#define REG_RX_IQC_AB_A 0x0c10
+#define REG_RX_IQC_CD_A 0x0c14
#define REG_TXSCALE_A 0x0c1c
#define BB_SWING_MASK GENMASK(31, 21)
#define REG_TX_AGC_A_CCK_11_CCK_1 0xc20
@@ -674,7 +707,7 @@
#define REG_LSSI_WRITE_A 0x0c90
#define REG_PREDISTA 0x0c90
#define REG_TXAGCIDX 0x0c94
-
+#define REG_TX_AGC_A 0x0c94
#define REG_RFE_PINMUX_A 0x0cb0
#define REG_RFE_INV_A 0x0cb4
#define REG_RFE_CTRL8 0x0cb4
@@ -683,6 +716,7 @@
#define DPDT_CTRL_PIN 0x77
#define RFE_INV_MASK 0x3ff00000
#define REG_RFECTL_A 0x0cb8
+#define REG_RFE_INV0 0x0cbc
#define REG_RFE_INV8 0x0cbd
#define BIT_MASK_RFE_INV89 GENMASK(1, 0)
#define REG_RFE_INV16 0x0cbe
@@ -703,6 +737,7 @@
#define REG_3WIRE_SWB 0x0e00
#define REG_RX_IQC_AB_B 0x0e10
+#define REG_RX_IQC_CD_B 0x0e14
#define REG_TXSCALE_B 0x0e1c
#define REG_TX_AGC_B_CCK_11_CCK_1 0xe20
#define REG_TX_AGC_B_OFDM18_OFDM6 0xe24
@@ -729,6 +764,7 @@
#define REG_LSSI_WRITE_B 0x0e90
#define REG_PREDISTB 0x0e90
#define REG_INIDLYB 0x0e94
+#define REG_TX_AGC_B 0x0e94
#define REG_RFE_PINMUX_B 0x0eb0
#define REG_RFE_INV_B 0x0eb4
#define REG_RFECTL_B 0x0eb8
@@ -744,8 +780,11 @@
#define REG_CRC_HT 0x0f10
#define REG_CRC_OFDM 0x0f14
#define REG_FA_OFDM 0x0f48
+#define REG_DBGRPT 0x0fa0
#define REG_CCA_CCK 0x0fcc
+#define REG_SYS_CFG3_8814A 0x1000
+
#define REG_ANAPARSW_MAC_0 0x1010
#define BIT_CF_L_V2 GENMASK(29, 28)
@@ -863,9 +902,27 @@
#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
+#define REG_RX_IQC_AB_C 0x1810
+#define REG_RX_IQC_CD_C 0x1814
+#define REG_TXSCALE_C 0x181c
+#define REG_CK_MONHC 0x185c
+#define REG_AFE_PWR1_C 0x1860
#define REG_IGN_GNT_BT1 0x1860
+#define REG_TX_AGC_C 0x1894
+#define REG_RFE_PINMUX_C 0x18b4
#define REG_RFESEL_CTRL 0x1990
+#define REG_AGC_TBL 0x1998
+
+#define REG_RX_IQC_AB_D 0x1a10
+#define REG_RX_IQC_CD_D 0x1a14
+#define REG_TXSCALE_D 0x1a1c
+#define REG_CK_MONHD 0x1a5c
+#define REG_AFE_PWR1_D 0x1a60
+#define REG_TX_AGC_D 0x1a94
+#define REG_RFE_PINMUX_D 0x1ab4
+#define REG_RFE_INVSEL_D 0x1abc
+#define BIT_RFE_SELSW0_D GENMASK(27, 20)
#define REG_NOMASK_TXBT 0x1ca7
#define REG_ANAPAR 0x1c30
@@ -906,6 +963,7 @@
#define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
#define RF18_CHANNEL_MASK (MASKBYTE0)
#define RF18_RFSI_MASK (BIT(18) | BIT(17))
+#define RF_RCK1_V1 0x1c
#define RF_RCK 0x1d
#define RF_MODE_TABLE_ADDR 0x30
#define RF_MODE_TABLE_DATA0 0x31
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