forked from Openwrt-EcoNet/openwrt
0ccc336c56
The original OF code effectively does a reset at ahb.c but then again in hw.c. For AR9330, it's already done in the driver and with the others, there are patches in here that do the same. hw.c looks like the proper place to handle this. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/19031 Signed-off-by: Robert Marko <robimarko@gmail.com>
167 lines
4.2 KiB
Diff
167 lines
4.2 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/init.c
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+++ b/drivers/net/wireless/ath/ath9k/init.c
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@@ -29,6 +29,11 @@
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#include "ath9k.h"
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+#ifdef CONFIG_ATH79
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+#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+#endif
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+
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struct ath9k_eeprom_ctx {
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struct completion complete;
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struct ath_hw *ah;
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@@ -243,6 +248,81 @@ static unsigned int ath9k_reg_rmw(void *
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return val;
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}
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+#ifdef CONFIG_ATH79
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+#define QCA955X_DDR_CTL_CONFIG 0x108
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+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
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+
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+static int ar913x_wmac_reset(void)
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+{
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+ ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
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+ mdelay(10);
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+
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+ ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
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+ mdelay(10);
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+
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+ return 0;
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+}
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+
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+static int ar933x_wmac_reset(void)
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+{
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+ int retries = 20;
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+
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+ ath79_device_reset_set(AR933X_RESET_WMAC);
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+ ath79_device_reset_clear(AR933X_RESET_WMAC);
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+
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+ while (1) {
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)
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+ return 0;
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+
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+ if (retries-- == 0)
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+ break;
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+
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+ udelay(10000);
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+ }
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+
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+ pr_err("ar933x: WMAC reset timed out");
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+ return -ETIMEDOUT;
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+}
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+
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+static int qca955x_wmac_reset(void)
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+{
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+ int i;
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+
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+ /* Try to wait for WMAC DDR activity to stop */
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+ for (i = 0; i < 10; i++) {
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+ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
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+ QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ ath79_device_reset_set(QCA955X_RESET_RTC);
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+ udelay(10);
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+ ath79_device_reset_clear(QCA955X_RESET_RTC);
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+ udelay(10);
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+
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+ return 0;
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+}
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+
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+
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+static int ar9330_get_soc_revision(void)
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+{
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+ if (ath79_soc_rev == 1)
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+ return ath79_soc_rev;
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+
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+ return 0;
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+}
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+
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+static int ath79_get_soc_revision(void)
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+{
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+ return ath79_soc_rev;
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+}
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+#endif
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+
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/**************************/
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/* Initialization */
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/**************************/
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@@ -670,6 +750,7 @@ static int ath9k_of_init(struct ath_soft
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struct ath_common *common = ath9k_hw_common(ah);
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enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
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char eeprom_name[100];
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+ u32 mask;
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int ret;
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if (!of_device_is_available(np))
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@@ -677,6 +758,43 @@ static int ath9k_of_init(struct ath_soft
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ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
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+ if (!of_property_read_u32(np, "qca,gpio-mask", &mask))
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+ ah->caps.gpio_mask = mask;
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+
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+ if (of_property_read_bool(np, "qca,tx-gain-buffalo"))
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+ ah->config.tx_gain_buffalo = true;
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+
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+#ifdef CONFIG_ATH79
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+ if (ah->hw_version.devid == AR5416_AR9100_DEVID) {
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+ ah->external_reset = ar913x_wmac_reset;
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+ } else if (ah->hw_version.devid == AR9300_DEVID_AR9330) {
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+ ah->get_mac_revision = ar9330_get_soc_revision;
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+ u32 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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+ ah->is_clk_25mhz = !(t & AR933X_BOOTSTRAP_REF_CLK_40);
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+ ah->external_reset = ar933x_wmac_reset;
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+ } else if (ah->hw_version.devid == AR9300_DEVID_AR9340) {
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+ ah->get_mac_revision = ath79_get_soc_revision;
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+ u32 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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+ ah->is_clk_25mhz = !(t & AR934X_BOOTSTRAP_REF_CLK_40);
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+ } else if (ah->hw_version.devid == AR9300_DEVID_AR953X) {
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+ ah->get_mac_revision = ath79_get_soc_revision;
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+ /*
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+ * QCA953x only supports 25MHz refclk.
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+ * Some vendors have an invalid bootstrap option
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+ * set, which would break the WMAC here.
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+ */
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+ ah->is_clk_25mhz = true;
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+ } else if (ah->hw_version.devid == AR9300_DEVID_QCA955X) {
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+ u32 t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
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+ ah->is_clk_25mhz = !(t & QCA955X_BOOTSTRAP_REF_CLK_40);
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+ ah->external_reset = qca955x_wmac_reset;
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+ } else if (ah->hw_version.devid == AR9300_DEVID_QCA956X) {
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+ ah->get_mac_revision = ath79_get_soc_revision;
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+ u32 t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
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+ ah->is_clk_25mhz = !(t & QCA956X_BOOTSTRAP_REF_CLK_40);
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+ }
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+#endif
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+
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if (of_property_read_bool(np, "qca,no-eeprom")) {
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/* ath9k-eeprom-<bus>-<id>.bin */
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scnprintf(eeprom_name, sizeof(eeprom_name),
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@@ -693,6 +811,17 @@ static int ath9k_of_init(struct ath_soft
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of_get_mac_address(np, common->macaddr);
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+ np = of_get_child_by_name(np, "led");
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+ if (np && of_device_is_available(np)) {
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+ u32 led_pin;
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+
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+ if (!of_property_read_u32(np, "led-sources", &led_pin))
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+ ah->led_pin = led_pin;
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+
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+ ah->config.led_active_high = !of_property_read_bool(np, "led-active-low");
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+ of_node_put(np);
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+ }
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+
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return 0;
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}
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