629 lines
20 KiB
Diff
629 lines
20 KiB
Diff
--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -295,6 +295,81 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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+static void __init qca953x_clocks_init(void)
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+{
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ath79_ref_clk.rate = 40 * 1000 * 1000;
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+ else
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+ ath79_ref_clk.rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
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+ ddr_pll /= (1 << out_div);
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+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CPU_DDR_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
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+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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+ else
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+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
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+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
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+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA953X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
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+ ath79_uart_clk.rate = ath79_ref_clk.rate;
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+}
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+
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static void __init qca955x_clocks_init(void)
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{
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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@@ -383,6 +490,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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+ else if (soc_is_qca953x())
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+ qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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else
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -72,7 +72,8 @@ void ath79_device_reset_set(u32 mask)
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x() ||
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- soc_is_qca955x())
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+ soc_is_qca953x() ||
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+ soc_is_qca955x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else
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BUG();
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@@ -99,7 +100,8 @@ void ath79_device_reset_clear(u32 mask)
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else if (soc_is_ar933x())
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x() ||
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- soc_is_qca955x())
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+ soc_is_qca953x() ||
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+ soc_is_qca955x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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else
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BUG();
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@@ -127,6 +129,8 @@ u32 ath79_device_reset_get(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else
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BUG();
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--- a/arch/mips/ath79/common.h
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+++ b/arch/mips/ath79/common.h
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@@ -29,6 +29,7 @@ void ath79_gpio_function_disable(u32 mas
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void ath79_gpio_function_setup(u32 set, u32 clear);
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void ath79_gpio_input_select(unsigned gpio, u8 val);
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void ath79_gpio_output_select(unsigned gpio, u8 val);
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+int ath79_gpio_direction_select(unsigned gpio, bool oe);
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void ath79_gpio_init(void);
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#endif /* __ATH79_COMMON_H */
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--- a/arch/mips/ath79/dev-common.c
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+++ b/arch/mips/ath79/dev-common.c
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@@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
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soc_is_ar724x() ||
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soc_is_ar913x() ||
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soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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soc_is_qca955x()) {
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ath79_uart_data[0].uartclk = clk_get_rate(clk);
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platform_device_register(&ath79_uart_device);
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--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -221,6 +221,29 @@ static void __init ar934x_usb_setup(void
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platform_device_register(&ath79_ehci_device);
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}
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+static void __init qca953x_usb_setup(void)
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+{
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+
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+ ath79_device_reset_set(QCA953X_RESET_USBSUS_OVERRIDE);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_PHY_ANALOG);
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+ udelay(1000);
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+
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+ ath79_device_reset_clear(QCA953X_RESET_USB_HOST);
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+ udelay(1000);
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+
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+ ath79_usb_init_resource(ath79_ehci0_resources, QCA953X_EHCI_BASE,
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+ QCA953X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
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+ ath79_ehci0_device.dev.platform_data = &ath79_ehci0_pdata_v2;
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+}
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+
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static void __init qca955x_usb_setup(void)
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{
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struct platform_device *pdev;
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@@ -277,6 +300,8 @@ void __init ath79_register_usb(void)
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ar933x_usb_setup();
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else if (soc_is_ar934x())
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ar934x_usb_setup();
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+ else if (soc_is_qca953x())
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+ qca953x_usb_setup();
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else if (soc_is_qca955x())
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qca955x_usb_setup();
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else
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -121,6 +121,24 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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+static void qca953x_wmac_setup(void)
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+{
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+ u32 t;
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+
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+ ath79_wmac_device.name = "qca953x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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+ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+
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+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+}
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+
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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@@ -232,7 +250,7 @@ bool __init ar93xx_wmac_read_mac_address
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u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
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int mac_start = 2, mac_end = 8;
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- BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
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+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x() && !soc_is_qca953x());
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base = ioremap_nocache(AR933X_WMAC_BASE, AR933X_WMAC_SIZE);
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while (addr > sizeof(hdr)) {
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if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr)))
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@@ -288,6 +306,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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+ else if (soc_is_qca953x())
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+ qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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else
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -131,6 +131,31 @@ static int ar934x_gpio_direction_output(
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return 0;
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}
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+int ath79_gpio_direction_select(unsigned gpio, bool oe)
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+{
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+ void __iomem *base = ath79_gpio_base;
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+ unsigned long flags;
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+ bool ieq_1 = (soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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+ soc_is_qca955x());
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+
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+ if (gpio >= ath79_gpio_count)
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+ return -1;
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+
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+ spin_lock_irqsave(&ath79_gpio_lock, flags);
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+
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+ if ((ieq_1 && oe) || (!ieq_1 && !oe))
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << gpio),
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+ base + AR71XX_GPIO_REG_OE);
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+ else
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+ __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << gpio),
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+ base + AR71XX_GPIO_REG_OE);
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+
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+ spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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static struct gpio_chip ath79_gpio_chip = {
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.label = "ath79",
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.get = ath79_gpio_get_value,
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@@ -149,7 +174,7 @@ static void __iomem *ath79_gpio_get_func
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soc_is_ar913x() ||
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soc_is_ar933x())
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reg = AR71XX_GPIO_REG_FUNC;
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- else if (soc_is_ar934x())
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+ else if (soc_is_ar934x() || soc_is_qca953x())
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reg = AR934X_GPIO_REG_FUNC;
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else
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BUG();
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@@ -208,7 +233,7 @@ void __init ath79_gpio_input_select(unsi
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BUG_ON(!soc_is_ar934x());
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- if (gpio >= AR934X_GPIO_COUNT)
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+ if (gpio >= ath79_gpio_count)
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return;
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reg = AR934X_GPIO_REG_IN_ENABLE0 + 4 * (val / 4);
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@@ -234,9 +259,9 @@ void __init ath79_gpio_output_select(uns
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unsigned int reg;
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u32 t, s;
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- BUG_ON(!soc_is_ar934x());
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+ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
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- if (gpio >= AR934X_GPIO_COUNT)
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+ if (gpio >= ath79_gpio_count)
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return;
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reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
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@@ -269,6 +294,8 @@ void __init ath79_gpio_init(void)
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ath79_gpio_count = AR933X_GPIO_COUNT;
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else if (soc_is_ar934x())
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ath79_gpio_count = AR934X_GPIO_COUNT;
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+ else if (soc_is_qca953x())
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+ ath79_gpio_count = QCA953X_GPIO_COUNT;
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else if (soc_is_qca955x())
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ath79_gpio_count = QCA955X_GPIO_COUNT;
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else
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@@ -276,7 +303,7 @@ void __init ath79_gpio_init(void)
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ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
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ath79_gpio_chip.ngpio = ath79_gpio_count;
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- if (soc_is_ar934x() || soc_is_qca955x()) {
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+ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
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ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
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ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
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}
|
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--- a/arch/mips/ath79/irq.c
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|
+++ b/arch/mips/ath79/irq.c
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|
@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
|
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
|
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soc_is_ar934x() ||
|
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+ soc_is_qca953x() ||
|
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soc_is_qca955x())
|
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
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else
|
|
@@ -153,6 +154,39 @@ static void ar934x_ip2_irq_init(void)
|
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irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
|
|
}
|
|
|
|
+static void qca953x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
|
+{
|
|
+ u32 status;
|
|
+
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+ disable_irq_nosync(irq);
|
|
+
|
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+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
|
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+
|
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+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
|
|
+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
|
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
|
|
+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
|
|
+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
|
|
+ generic_handle_irq(ATH79_IP2_IRQ(1));
|
|
+ } else {
|
|
+ spurious_interrupt();
|
|
+ }
|
|
+
|
|
+ enable_irq(irq);
|
|
+}
|
|
+
|
|
+static void qca953x_irq_init(void)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ for (i = ATH79_IP2_IRQ_BASE;
|
|
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
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+ irq_set_chip_and_handler(i, &dummy_irq_chip,
|
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+ handle_level_irq);
|
|
+
|
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+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca953x_ip2_irq_dispatch);
|
|
+}
|
|
+
|
|
static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
|
|
{
|
|
u32 status;
|
|
@@ -335,6 +369,12 @@ static void ar934x_ip3_handler(void)
|
|
do_IRQ(ATH79_CPU_IRQ_USB);
|
|
}
|
|
|
|
+static void qca953x_ip3_handler(void)
|
|
+{
|
|
+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_USB);
|
|
+ do_IRQ(ATH79_CPU_IRQ_USB);
|
|
+}
|
|
+
|
|
void __init arch_init_irq(void)
|
|
{
|
|
if (soc_is_ar71xx()) {
|
|
@@ -352,6 +392,9 @@ void __init arch_init_irq(void)
|
|
} else if (soc_is_ar934x()) {
|
|
ath79_ip2_handler = ath79_default_ip2_handler;
|
|
ath79_ip3_handler = ar934x_ip3_handler;
|
|
+ } else if (soc_is_qca953x()) {
|
|
+ ath79_ip2_handler = ath79_default_ip2_handler;
|
|
+ ath79_ip3_handler = qca953x_ip3_handler;
|
|
} else if (soc_is_qca955x()) {
|
|
ath79_ip2_handler = ath79_default_ip2_handler;
|
|
ath79_ip3_handler = ath79_default_ip3_handler;
|
|
@@ -365,6 +408,8 @@ void __init arch_init_irq(void)
|
|
|
|
if (soc_is_ar934x())
|
|
ar934x_ip2_irq_init();
|
|
+ else if (soc_is_qca953x())
|
|
+ qca953x_irq_init();
|
|
else if (soc_is_qca955x())
|
|
qca955x_irq_init();
|
|
}
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -115,6 +115,15 @@
|
|
#define AR934X_NFC_BASE 0x1b000200
|
|
#define AR934X_NFC_SIZE 0xb8
|
|
|
|
+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define QCA953X_GMAC_SIZE 0x14
|
|
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
+#define QCA953X_WMAC_SIZE 0x20000
|
|
+#define QCA953X_EHCI_BASE 0x1b000000
|
|
+#define QCA953X_EHCI_SIZE 0x200
|
|
+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
|
+#define QCA953X_SRIF_SIZE 0x1000
|
|
+
|
|
#define QCA955X_PCI_MEM_BASE0 0x10000000
|
|
#define QCA955X_PCI_MEM_BASE1 0x12000000
|
|
#define QCA955X_PCI_MEM_SIZE 0x02000000
|
|
@@ -183,6 +192,12 @@
|
|
#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
|
|
#define AR934X_DDR_REG_FLUSH_WMAC 0xac
|
|
|
|
+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
|
|
+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
|
|
+#define QCA953X_DDR_REG_FLUSH_USB 0xa4
|
|
+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
|
|
+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
|
|
+
|
|
/*
|
|
* PLL block
|
|
*/
|
|
@@ -291,6 +306,45 @@
|
|
|
|
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
|
|
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
|
|
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
|
|
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
+
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
|
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
|
|
+
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
|
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
|
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
|
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
|
+
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
+#define QCA953X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
+
|
|
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
+
|
|
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
@@ -379,6 +433,10 @@
|
|
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
|
|
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
|
|
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
|
|
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
+
|
|
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
|
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
|
|
|
@@ -473,6 +531,27 @@
|
|
#define AR934X_RESET_MBOX BIT(1)
|
|
#define AR934X_RESET_I2S BIT(0)
|
|
|
|
+#define QCA953X_RESET_USB_EXT_PWR BIT(29)
|
|
+#define QCA953X_RESET_EXTERNAL BIT(28)
|
|
+#define QCA953X_RESET_RTC BIT(27)
|
|
+#define QCA953X_RESET_FULL_CHIP BIT(24)
|
|
+#define QCA953X_RESET_GE1_MDIO BIT(23)
|
|
+#define QCA953X_RESET_GE0_MDIO BIT(22)
|
|
+#define QCA953X_RESET_CPU_NMI BIT(21)
|
|
+#define QCA953X_RESET_CPU_COLD BIT(20)
|
|
+#define QCA953X_RESET_DDR BIT(16)
|
|
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
|
+#define QCA953X_RESET_GE1_MAC BIT(13)
|
|
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
|
|
+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
|
|
+#define QCA953X_RESET_GE0_MAC BIT(9)
|
|
+#define QCA953X_RESET_ETH_SWITCH BIT(8)
|
|
+#define QCA953X_RESET_PCIE_PHY BIT(7)
|
|
+#define QCA953X_RESET_PCIE BIT(6)
|
|
+#define QCA953X_RESET_USB_HOST BIT(5)
|
|
+#define QCA953X_RESET_USB_PHY BIT(4)
|
|
+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
|
|
+
|
|
#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
|
|
#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
|
|
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
|
@@ -493,6 +572,13 @@
|
|
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
|
|
|
+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
|
|
+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
|
|
+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
|
|
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
|
|
+
|
|
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
@@ -513,6 +599,24 @@
|
|
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
|
|
AR934X_PCIE_WMAC_INT_PCIE_RC3)
|
|
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
|
|
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
|
|
+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
|
|
+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
|
|
+
|
|
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
|
|
+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
|
|
+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
|
|
+ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
|
|
+
|
|
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
|
|
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
|
|
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
|
|
@@ -652,11 +756,31 @@
|
|
#define AR934X_GPIO_IN_MUX_I2S_ETH_RX_COL 9
|
|
#define AR934X_GPIO_IN_MUX_I2S_ETH_RX_CRS 10
|
|
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
|
|
+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
|
|
+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
|
|
+#define QCA953X_GPIO_REG_FUNC 0x6c
|
|
+
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
|
|
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
|
|
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
|
|
+
|
|
#define AR71XX_GPIO_COUNT 16
|
|
#define AR724X_GPIO_COUNT 18
|
|
#define AR913X_GPIO_COUNT 22
|
|
#define AR933X_GPIO_COUNT 30
|
|
#define AR934X_GPIO_COUNT 23
|
|
+#define QCA953X_GPIO_COUNT 18
|
|
#define QCA955X_GPIO_COUNT 24
|
|
|
|
/*
|
|
@@ -680,6 +804,24 @@
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
|
|
|
|
+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
|
|
+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
|
|
+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
|
|
+
|
|
+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
|
|
+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
|
|
+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
|
|
+
|
|
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
|
|
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
|
|
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
|
|
+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
|
|
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
|
|
+
|
|
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
|
|
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
|
|
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
|
|
+
|
|
#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
|
|
#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
|
|
#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
|
|
@@ -802,9 +944,19 @@
|
|
#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
|
#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
|
#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
|
|
-#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
|
|
+#define AR934X_ETH_CFG_MII_CNTL_SPEED BIT(11)
|
|
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
|
|
-#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
|
+#define AR934X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
|
+
|
|
+/*
|
|
+ * QCA953X GMAC Interface
|
|
+ */
|
|
+#define QCA953X_GMAC_REG_ETH_CFG 0x00
|
|
+
|
|
+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
|
|
+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
|
+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
|
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
|
|
|
/*
|
|
* QCA955X GMAC Interface
|