mirror of
https://github.com/merbanan/airoha_ml.git
synced 2025-11-10 16:36:41 +00:00
440 lines
9.1 KiB
Plaintext
440 lines
9.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/en7523-clk.h>
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#include <dt-bindings/leds/common.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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npu_binary@84000000 {
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no-map;
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reg = <0x84000000 0xA00000>;
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};
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npu_flag@84B0000 {
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no-map;
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reg = <0x84B00000 0x100000>;
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};
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npu_pkt@85000000 {
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no-map;
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reg = <0x85000000 0x1A00000>;
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};
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npu_phyaddr@86B00000 {
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no-map;
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reg = <0x86B00000 0x100000>;
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};
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npu_rxdesc@86D00000 {
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no-map;
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reg = <0x86D00000 0x100000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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clock-frequency = <80000000>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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scu: system-controller@1fa20000 {
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compatible = "airoha,en7523-scu";
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reg = <0x1fa20000 0x4>,
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<0x1fb00000 0x4>;
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#clock-cells = <1>;
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};
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gic: interrupt-controller@9000000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x09000000 0x20000>,
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<0x09080000 0x80000>,
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<0x09400000 0x2000>,
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<0x09500000 0x2000>,
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<0x09600000 0x20000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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uart1: serial@1fbf0000 {
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compatible = "ns16550";
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reg = <0x1fbf0000 0x30>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <1843200>;
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status = "okay";
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};
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gpio0: gpio@1fbf0200 {
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compatible = "airoha,en7523-gpio";
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reg = <0x1fbf0204 0x4>,
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<0x1fbf0200 0x4>,
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<0x1fbf0220 0x4>,
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<0x1fbf0214 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1fbf0270 {
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compatible = "airoha,en7523-gpio";
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reg = <0x1fbf0270 0x4>,
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<0x1fbf0260 0x4>,
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<0x1fbf0264 0x4>,
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<0x1fbf0278 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pcie0: pcie@1fa91000 {
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compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0x1fa91000 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&scu EN7523_CLK_PCIE>;
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clock-names = "sys_ck0";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1: pcie@1fa92000 {
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compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0x1fa92000 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&scu EN7523_CLK_PCIE>;
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clock-names = "sys_ck1";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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spi_ctrl: spi_controller@1fa10000 {
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compatible = "airoha,en7523-spi";
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reg = <0x1fa10000 0x140>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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nand: nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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nand-ecc-engine = <&nand>;
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};
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};
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eth: ethernet@15100000 {
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compatible = "airoha,en7523-eth";
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reg = <0x1fb50000 0x2600>, //FE + PPE
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<0x1fb54000 0x2000>, //QDMA1
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<0x1fb56000 0x2000>, //QDMA2
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<0x1FB00834 0x4>; //RST
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT1 21+16
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT2 39+16
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT3 40+16
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, // QDMA LAN INT4 41+16
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT1 22+16
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT2 42+16
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT3 43+16
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, // QDMA WAN INT4 44+16
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, // FE ERROR INTR 33+16
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<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; // PDMA INTR 48+16
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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hsmac0: mac@0 {
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compatible = "airoha,xsi-mac";
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reg = <0x1fa60000 0x210>; // AE/(PON)
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status = "disabled";
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};
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hsmac1: mac@1 {
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compatible = "airoha,xsi-mac";
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reg = <0x1fa70000 0x210>; // PCIE0
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status = "disabled";
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};
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hsmac2: mac@2 {
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compatible = "airoha,xsi-mac";
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reg = <0x1fa71000 0x210>; // PCIE1
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status = "disabled";
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};
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hsmac3: mac@3 {
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compatible = "airoha,xsi-mac";
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reg = <0x1fa80000 0x210>; // USB_BASE
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status = "disabled";
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};
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ethrst: reset-controller {
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compatible = "ti,syscon-reset";
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#reset-cells = <1>;
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};
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switch1: switch@1fb58000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "airoha,en7523-switch";
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reg = <0x1fb58000 0x8000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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resets = <ðrst 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_port1: port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&gsw_phy1>;
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};
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gsw_port2: port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&gsw_phy2>;
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};
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gsw_port3: port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&gsw_phy3>;
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};
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gsw_port4: port@4 {
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reg = <4>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&gsw_phy4>;
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <9>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy1_led0: gsw-phy1-led0@0 {
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reg = <0>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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gsw_phy1_led1: gsw-phy1-led1@1 {
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reg = <1>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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};
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};
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gsw_phy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <10>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy2_led0: gsw-phy2-led0@0 {
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reg = <0>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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gsw_phy2_led1: gsw-phy2-led1@1 {
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reg = <1>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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};
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};
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gsw_phy3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <11>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy3_led0: gsw-phy3-led0@0 {
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reg = <0>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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gsw_phy3_led1: gsw-phy3-led1@1 {
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reg = <1>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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};
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};
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gsw_phy4: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <12>;
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phy-mode = "internal";
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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gsw_phy4_led0: gsw-phy4-led0@0 {
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reg = <0>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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gsw_phy4_led1: gsw-phy4-led1@1 {
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reg = <1>;
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function = LED_FUNCTION_LAN;
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status = "disabled";
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};
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};
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};
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};
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};
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};
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