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airoha_ml/0015-AN7581-pinmux-driver.patch
Benjamin Larsson 92f7959aa1 Random driver code
2024-05-05 23:53:56 +02:00

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From 9065ab9d66cbeb4813eac2721c8148ddb409eaa3 Mon Sep 17 00:00:00 2001
From: Benjamin Larsson <benjamin.larsson@genexis.eu>
Date: Wed, 29 Nov 2023 11:25:07 +0100
Subject: [PATCH] AN7581 pinmux driver
---
drivers/pinctrl/Makefile | 3 +-
drivers/pinctrl/pinctrl-an7581.c | 2445 ++++++++++++++++++++++++++++++
2 files changed, 2446 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-an7581.c
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f58d750b2..72906da59 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -46,8 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
-obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-en7523.o
-
+obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-en7523.o pinctrl-an7581.o
obj-y += actions/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
diff --git a/drivers/pinctrl/pinctrl-an7581.c b/drivers/pinctrl/pinctrl-an7581.c
new file mode 100644
index 000000000..35a64e6f9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-an7581.c
@@ -0,0 +1,2445 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Airoha AN7581 pin-crtl driver.
+ *
+ * Copyright (c) 2023 Genexis Sweden AB
+ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
+ *
+ * Based on pinctrl-artpec6.c
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/slab.h>
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+/* Pin drive strength options */
+#define AN7581_DRIVE_2mA 2
+#define AN7581_DRIVE_2mA_SET 0
+#define AN7581_DRIVE_4mA 4
+#define AN7581_DRIVE_4mA_SET 1
+#define AN7581_DRIVE_6mA 6
+#define AN7581_DRIVE_6mA_SET 2
+#define AN7581_DRIVE_8mA 8
+#define AN7581_DRIVE_8mA_SET 3
+
+/* Load the relevant 32 bit registers from dts in the enumeration order
+ */
+
+enum register_names {
+ IOMUX1=0,
+ IOMUX2,
+ IOMUX3,
+ IOMUX4,
+ IOMUX5,
+ IOMUX6,
+ IOMUX7,
+ IOMUX_RESERVE1,
+ IO_DRIVE_CTRL1,
+ IO_DRIVE_CTRL2,
+ GPIO_LB_DRIVE_CTRL1,
+ GPIO_LB_DRIVE_CTRL2,
+ GPIO_HB_DRIVE_CTRL1,
+ GPIO_HB_DRIVE_CTRL2,
+ IO_PULL_UP_CTRL1,
+ IO_PULL_DOWN_CTRL2,
+ GPIO_LB_PULL_UP_CTRL,
+ GPIO_LB_PULL_DOWN_CTRL,
+ GPIO_HB_PULL_UP_CTRL,
+ GPIO_HB_PULL_DOWN_CTRL,
+ LED0_MAP,
+ LED1_MAP,
+ MUX_REG_MAX,
+};
+
+#define MAX_CONFIGS 4
+
+struct an7581_pmx {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *mux_regs[MUX_REG_MAX];
+ struct pinctrl_pin_desc *pins;
+ unsigned int num_pins;
+ const struct an7581_pin_group *pin_groups;
+ unsigned int num_pin_groups;
+ const struct an7581_pmx_func *functions;
+ unsigned int num_functions;
+};
+
+struct an7581_pin_group {
+ const char *name;
+ const int *pins;
+ const unsigned int num_pins;
+};
+
+struct an7581_pmx_func {
+ const char *name;
+ const char * const *groups;
+ const unsigned int num_groups;
+ const int configs[MAX_CONFIGS];
+ const unsigned int num_configs;
+ const int unset;
+};
+
+struct an7581_pin_setting {
+ int pin_idx;
+ const unsigned int pull_up;
+ const unsigned int pull_down;
+ const unsigned int drive_e2;
+ const unsigned int drive_e4;
+ const unsigned int gpio;
+};
+
+struct mux_reg {
+ int reg_id;
+ int reg_idx;
+ u32 reg_mask;
+};
+
+enum reg_names {
+ RG_REG_NULL=0,
+ // IOMUX Control 1 Register
+ RG_GPIO_MDC_IO_MASTER_MODE,
+ RG_GPIO_I2C_MASTER_MODE,
+ RG_GPIO_I2S_MODE,
+ RG_GPIO_I2C_SLAVE_MODE,
+ RG_GPIO_LAN3_LED1_MODE,
+ RG_GPIO_LAN3_LED0_MODE,
+ RG_GPIO_LAN2_LED1_MODE,
+ RG_GPIO_LAN2_LED0_MODE,
+ RG_GPIO_LAN1_LED1_MODE,
+ RG_GPIO_LAN1_LED0_MODE,
+ RG_GPIO_LAN0_LED1_MODE,
+ RG_GPIO_LAN0_LED0_MODE,
+ RG_PON_TOD_1PPS_MODE,
+ RG_SW_TOD_1PPS_MODE,
+ RG_GPIO_2ND_I2C_MODE,
+
+ // IOMUX Control 2 Register
+ RG_GPIO_PCM_SPI_CS4_MODE,
+ RG_GPIO_PCM_SPI_CS3_MODE,
+ RG_GPIO_PCM_SPI_CS2_MODE_156PIN,
+ RG_GPIO_PCM_SPI_CS2_MODE_128PIN,
+ RG_GPIO_PCM_SPI_CS1_MODE,
+ RG_GPIO_PCM_SPI_MODE,
+ RG_GPIO_PCM2_MODE,
+ RG_GPIO_PCM1_MODE,
+ RG_GPIO_PCM_INT_MODE,
+ RG_GPIO_PCM_RESET_MODE,
+ RG_GPIO_SPI_QUAD_MODE,
+ RG_GPIO_SPI_CS1_MODE,
+
+ // IOMUX Control 3 Register
+ RG_GPIO_PARALLEL_NAND_MODE,
+ RG_GPIO_SGMII_MDIO_MODE,
+ RG_PCIE_RESET2_GPIO_MODE,
+ RG_SIPO_RCLK_MODE,
+ RG_PCIE_RESET1_GPIO_MODE,
+ RG_PCIE_RESET0_GPIO_MODE,
+ RG_GPIO_UART5_MODE,
+ RG_GPIO_UART4_MODE,
+ RG_GPIO_HSUART3_CTS_RTS_MODE,
+ RG_GPIO_HSUART3_MODE,
+ RG_GPIO_UART2_CTS_RTS_MODE,
+ RG_GPIO_UART2_MODE,
+ RG_SIPO_MODE,
+ RG_GPIO_EMMC_MODE,
+ RG_GPIO_PON_MODE,
+
+ // IOMUX Control 5 Register
+ RG_UDI_EJTAG_EN,
+ RG_DFD_EJTAG_EN,
+ RG_NPU_UART_EN,
+
+ // IOMUX Control 6 Register
+ RG_FORCE_GPIO31_EN,
+ RG_FORCE_GPIO30_EN,
+ RG_FORCE_GPIO29_EN,
+ RG_FORCE_GPIO28_EN,
+ RG_FORCE_GPIO27_EN,
+ RG_FORCE_GPIO26_EN,
+ RG_FORCE_GPIO25_EN,
+ RG_FORCE_GPIO24_EN,
+ RG_FORCE_GPIO23_EN,
+ RG_FORCE_GPIO22_EN,
+ RG_FORCE_GPIO21_EN,
+ RG_FORCE_GPIO20_EN,
+ RG_FORCE_GPIO19_EN,
+ RG_FORCE_GPIO18_EN,
+ RG_FORCE_GPIO17_EN,
+ RG_FORCE_GPIO16_EN,
+ RG_FORCE_GPIO15_EN,
+ RG_FORCE_GPIO14_EN,
+ RG_FORCE_GPIO13_EN,
+ RG_FORCE_GPIO12_EN,
+ RG_FORCE_GPIO11_EN,
+ RG_FORCE_GPIO10_EN,
+ RG_FORCE_GPIO9_EN,
+ RG_FORCE_GPIO8_EN,
+ RG_FORCE_GPIO7_EN,
+ RG_FORCE_GPIO6_EN,
+ RG_FORCE_GPIO5_EN,
+ RG_FORCE_GPIO4_EN,
+ RG_FORCE_GPIO3_EN,
+ RG_FORCE_GPIO2_EN,
+ RG_FORCE_GPIO1_EN,
+ RG_FORCE_GPIO0_EN, // reseved
+
+ // IOMUX Control 7 Register
+ RG_FORCE_GPIO46_EN,
+ RG_FORCE_GPIO45_EN,
+ RG_FORCE_GPIO44_EN,
+ RG_FORCE_GPIO43_EN,
+ RG_FORCE_GPIO42_EN,
+ RG_FORCE_GPIO41_EN,
+ RG_FORCE_GPIO40_EN,
+ RG_FORCE_GPIO39_EN,
+ RG_FORCE_GPIO38_EN,
+ RG_FORCE_GPIO37_EN,
+ RG_FORCE_GPIO36_EN,
+ RG_FORCE_GPIO35_EN,
+ RG_FORCE_GPIO34_EN,
+ RG_FORCE_GPIO33_EN,
+ RG_FORCE_GPIO32_EN,
+
+ // IOMUX Reserve 1 Register
+ RG_INIC_MDIO2OCP_MODE_SEL,
+ RG_INIC_MDIO_SLAVE_MODE,
+
+ // LED0 Mapping Register
+ RG_LAN3_LED0_MAPPING_LAN0,
+ RG_LAN3_LED0_MAPPING_LAN1,
+ RG_LAN3_LED0_MAPPING_LAN2,
+ RG_LAN3_LED0_MAPPING_LAN3,
+ RG_LAN3_LED0_MAPPING_LAN4,
+ RG_LAN2_LED0_MAPPING_LAN0,
+ RG_LAN2_LED0_MAPPING_LAN1,
+ RG_LAN2_LED0_MAPPING_LAN2,
+ RG_LAN2_LED0_MAPPING_LAN3,
+ RG_LAN2_LED0_MAPPING_LAN4,
+ RG_LAN1_LED0_MAPPING_LAN0,
+ RG_LAN1_LED0_MAPPING_LAN1,
+ RG_LAN1_LED0_MAPPING_LAN2,
+ RG_LAN1_LED0_MAPPING_LAN3,
+ RG_LAN1_LED0_MAPPING_LAN4,
+ RG_LAN0_LED0_MAPPING_LAN0,
+ RG_LAN0_LED0_MAPPING_LAN1,
+ RG_LAN0_LED0_MAPPING_LAN2,
+ RG_LAN0_LED0_MAPPING_LAN3,
+ RG_LAN0_LED0_MAPPING_LAN4,
+
+ // LED1 Mapping Register
+ RG_LAN3_LED1_MAPPING_LAN0,
+ RG_LAN3_LED1_MAPPING_LAN1,
+ RG_LAN3_LED1_MAPPING_LAN2,
+ RG_LAN3_LED1_MAPPING_LAN3,
+ RG_LAN3_LED1_MAPPING_LAN4,
+ RG_LAN2_LED1_MAPPING_LAN0,
+ RG_LAN2_LED1_MAPPING_LAN1,
+ RG_LAN2_LED1_MAPPING_LAN2,
+ RG_LAN2_LED1_MAPPING_LAN3,
+ RG_LAN2_LED1_MAPPING_LAN4,
+ RG_LAN1_LED1_MAPPING_LAN0,
+ RG_LAN1_LED1_MAPPING_LAN1,
+ RG_LAN1_LED1_MAPPING_LAN2,
+ RG_LAN1_LED1_MAPPING_LAN3,
+ RG_LAN1_LED1_MAPPING_LAN4,
+ RG_LAN0_LED1_MAPPING_LAN0,
+ RG_LAN0_LED1_MAPPING_LAN1,
+ RG_LAN0_LED1_MAPPING_LAN2,
+ RG_LAN0_LED1_MAPPING_LAN3,
+ RG_LAN0_LED1_MAPPING_LAN4,
+
+ // IO TX Driving Control 1
+ RG_SPI_MISO_E2,
+ RG_SPI_MOSI_E2,
+ RG_SPI_CLK_E2,
+ RG_SPI_CS0_E2,
+ RG_PCIE2_RESET_E2,
+ RG_PCIE1_RESET_E2,
+ RG_PCIE0_RESET_E2,
+ RG_UART1_RXD_E2,
+ RG_UART1_TXD_E2,
+ RG_I2C_SCL_E2,
+ RG_I2C_SDA_E2,
+
+ // IO TX Driving Control 2
+ RG_SPI_MISO_E4,
+ RG_SPI_MOSI_E4,
+ RG_SPI_CLK_E4,
+ RG_SPI_CS0_E4,
+ RG_PCIE2_RESET_E4,
+ RG_PCIE1_RESET_E4,
+ RG_PCIE0_RESET_E4,
+ RG_UART1_RXD_E4,
+ RG_UART1_TXD_E4,
+ RG_I2C_SCL_E4,
+ RG_I2C_SDA_E4,
+
+ // GPIO TX Driving Control 1
+ RG_GPIO0_L_E2,
+ RG_GPIO1_L_E2,
+ RG_GPIO2_L_E2,
+ RG_GPIO3_L_E2,
+ RG_GPIO4_L_E2,
+ RG_GPIO5_L_E2,
+ RG_GPIO6_L_E2,
+ RG_GPIO7_L_E2,
+ RG_GPIO8_L_E2,
+ RG_GPIO9_L_E2,
+ RG_GPIO10_L_E2,
+ RG_GPIO11_L_E2,
+ RG_GPIO12_L_E2,
+ RG_GPIO13_L_E2,
+ RG_GPIO14_L_E2,
+ RG_GPIO15_L_E2,
+ RG_GPIO16_L_E2,
+ RG_GPIO17_L_E2,
+ RG_GPIO18_L_E2,
+ RG_GPIO19_L_E2,
+ RG_GPIO20_L_E2,
+ RG_GPIO21_L_E2,
+ RG_GPIO22_L_E2,
+ RG_GPIO23_L_E2,
+ RG_GPIO24_L_E2,
+ RG_GPIO25_L_E2,
+ RG_GPIO26_L_E2,
+ RG_GPIO27_L_E2,
+ RG_GPIO28_L_E2,
+ RG_GPIO29_L_E2,
+ RG_GPIO30_L_E2,
+ RG_GPIO31_L_E2,
+
+ // GPIO TX Driving Control 2
+ RG_GPIO0_L_E4,
+ RG_GPIO1_L_E4,
+ RG_GPIO2_L_E4,
+ RG_GPIO3_L_E4,
+ RG_GPIO4_L_E4,
+ RG_GPIO5_L_E4,
+ RG_GPIO6_L_E4,
+ RG_GPIO7_L_E4,
+ RG_GPIO8_L_E4,
+ RG_GPIO9_L_E4,
+ RG_GPIO10_L_E4,
+ RG_GPIO11_L_E4,
+ RG_GPIO12_L_E4,
+ RG_GPIO13_L_E4,
+ RG_GPIO14_L_E4,
+ RG_GPIO15_L_E4,
+ RG_GPIO16_L_E4,
+ RG_GPIO17_L_E4,
+ RG_GPIO18_L_E4,
+ RG_GPIO19_L_E4,
+ RG_GPIO20_L_E4,
+ RG_GPIO21_L_E4,
+ RG_GPIO22_L_E4,
+ RG_GPIO23_L_E4,
+ RG_GPIO24_L_E4,
+ RG_GPIO25_L_E4,
+ RG_GPIO26_L_E4,
+ RG_GPIO27_L_E4,
+ RG_GPIO28_L_E4,
+ RG_GPIO29_L_E4,
+ RG_GPIO30_L_E4,
+ RG_GPIO31_L_E4,
+
+ // GPIO higher byte TX Driving Control 1
+ RG_GPIO32_H_E2,
+ RG_GPIO33_H_E2,
+ RG_GPIO34_H_E2,
+ RG_GPIO35_H_E2,
+ RG_GPIO36_H_E2,
+ RG_GPIO37_H_E2,
+ RG_GPIO38_H_E2,
+ RG_GPIO39_H_E2,
+ RG_GPIO40_H_E2,
+ RG_GPIO41_H_E2,
+ RG_GPIO42_H_E2,
+ RG_GPIO43_H_E2,
+ RG_GPIO44_H_E2,
+ RG_GPIO45_H_E2,
+ RG_GPIO46_H_E2,
+
+ // GPIO higher byte TX Driving Control 2
+ RG_GPIO32_H_E4,
+ RG_GPIO33_H_E4,
+ RG_GPIO34_H_E4,
+ RG_GPIO35_H_E4,
+ RG_GPIO36_H_E4,
+ RG_GPIO37_H_E4,
+ RG_GPIO38_H_E4,
+ RG_GPIO39_H_E4,
+ RG_GPIO40_H_E4,
+ RG_GPIO41_H_E4,
+ RG_GPIO42_H_E4,
+ RG_GPIO43_H_E4,
+ RG_GPIO44_H_E4,
+ RG_GPIO45_H_E4,
+ RG_GPIO46_H_E4,
+
+ // IO Pull Up Control 1
+ RG_SPI_MISO_PU,
+ RG_SPI_MOSI_PU,
+ RG_SPI_CLK_PU,
+ RG_SPI_CS0_PU,
+ RG_PCIE2_RESET_PU,
+ RG_PCIE1_RESET_PU,
+ RG_PCIE0_RESET_PU,
+ RG_UART1_RXD_PU,
+ RG_UART1_TXD_PU,
+ RG_I2C_SCL_PU,
+ RG_I2C_SDA_PU,
+
+ // IO Pull Down Control 2
+ RG_SPI_MISO_PD,
+ RG_SPI_MOSI_PD,
+ RG_SPI_CLK_PD,
+ RG_SPI_CS0_PD,
+ RG_PCIE2_RESET_PD,
+ RG_PCIE1_RESET_PD,
+ RG_PCIE0_RESET_PD,
+ RG_UART1_RXD_PD,
+ RG_UART1_TXD_PD,
+ RG_I2C_SCL_PD,
+ RG_I2C_SDA_PD,
+
+ // GPIO lower byte Pull Up Control
+ RG_GPIO0_L_PU,
+ RG_GPIO1_L_PU,
+ RG_GPIO2_L_PU,
+ RG_GPIO3_L_PU,
+ RG_GPIO4_L_PU,
+ RG_GPIO5_L_PU,
+ RG_GPIO6_L_PU,
+ RG_GPIO7_L_PU,
+ RG_GPIO8_L_PU,
+ RG_GPIO9_L_PU,
+ RG_GPIO10_L_PU,
+ RG_GPIO11_L_PU,
+ RG_GPIO12_L_PU,
+ RG_GPIO13_L_PU,
+ RG_GPIO14_L_PU,
+ RG_GPIO15_L_PU,
+ RG_GPIO16_L_PU,
+ RG_GPIO17_L_PU,
+ RG_GPIO18_L_PU,
+ RG_GPIO19_L_PU,
+ RG_GPIO20_L_PU,
+ RG_GPIO21_L_PU,
+ RG_GPIO22_L_PU,
+ RG_GPIO23_L_PU,
+ RG_GPIO24_L_PU,
+ RG_GPIO25_L_PU,
+ RG_GPIO26_L_PU,
+ RG_GPIO27_L_PU,
+ RG_GPIO28_L_PU,
+ RG_GPIO29_L_PU,
+ RG_GPIO30_L_PU,
+ RG_GPIO31_L_PU,
+
+ // GPIO higher byte Pull Up Control
+ RG_GPIO32_H_PU,
+ RG_GPIO33_H_PU,
+ RG_GPIO34_H_PU,
+ RG_GPIO35_H_PU,
+ RG_GPIO36_H_PU,
+ RG_GPIO37_H_PU,
+ RG_GPIO38_H_PU,
+ RG_GPIO39_H_PU,
+ RG_GPIO40_H_PU,
+ RG_GPIO41_H_PU,
+ RG_GPIO42_H_PU,
+ RG_GPIO43_H_PU,
+ RG_GPIO44_H_PU,
+ RG_GPIO45_H_PU,
+ RG_GPIO46_H_PU,
+
+
+ // GPIO lower byte Pull Down Control
+ RG_GPIO0_L_PD,
+ RG_GPIO1_L_PD,
+ RG_GPIO2_L_PD,
+ RG_GPIO3_L_PD,
+ RG_GPIO4_L_PD,
+ RG_GPIO5_L_PD,
+ RG_GPIO6_L_PD,
+ RG_GPIO7_L_PD,
+ RG_GPIO8_L_PD,
+ RG_GPIO9_L_PD,
+ RG_GPIO10_L_PD,
+ RG_GPIO11_L_PD,
+ RG_GPIO12_L_PD,
+ RG_GPIO13_L_PD,
+ RG_GPIO14_L_PD,
+ RG_GPIO15_L_PD,
+ RG_GPIO16_L_PD,
+ RG_GPIO17_L_PD,
+ RG_GPIO18_L_PD,
+ RG_GPIO19_L_PD,
+ RG_GPIO20_L_PD,
+ RG_GPIO21_L_PD,
+ RG_GPIO22_L_PD,
+ RG_GPIO23_L_PD,
+ RG_GPIO24_L_PD,
+ RG_GPIO25_L_PD,
+ RG_GPIO26_L_PD,
+ RG_GPIO27_L_PD,
+ RG_GPIO28_L_PD,
+ RG_GPIO29_L_PD,
+ RG_GPIO30_L_PD,
+ RG_GPIO31_L_PD,
+
+ // GPIO higher byte Pull Down Control
+ RG_GPIO32_H_PD,
+ RG_GPIO33_H_PD,
+ RG_GPIO34_H_PD,
+ RG_GPIO35_H_PD,
+ RG_GPIO36_H_PD,
+ RG_GPIO37_H_PD,
+ RG_GPIO38_H_PD,
+ RG_GPIO39_H_PD,
+ RG_GPIO40_H_PD,
+ RG_GPIO41_H_PD,
+ RG_GPIO42_H_PD,
+ RG_GPIO43_H_PD,
+ RG_GPIO44_H_PD,
+ RG_GPIO45_H_PD,
+ RG_GPIO46_H_PD,
+
+ RG_REG_NAME_MAX,
+};
+
+static const struct mux_reg an7581_registers[] = {
+ // IOMUX Control 1 Register
+ { RG_GPIO_MDC_IO_MASTER_MODE, IOMUX1, 1<<14},
+ { RG_GPIO_I2C_MASTER_MODE, IOMUX1, 1<<13},
+ { RG_GPIO_I2S_MODE, IOMUX1, 1<<12},
+ { RG_GPIO_I2C_SLAVE_MODE, IOMUX1, 1<<11},
+ { RG_GPIO_LAN3_LED1_MODE, IOMUX1, 1<<10},
+ { RG_GPIO_LAN3_LED0_MODE, IOMUX1, 1<<9},
+ { RG_GPIO_LAN2_LED1_MODE, IOMUX1, 1<<8},
+ { RG_GPIO_LAN2_LED0_MODE, IOMUX1, 1<<7},
+ { RG_GPIO_LAN1_LED1_MODE, IOMUX1, 1<<6},
+ { RG_GPIO_LAN1_LED0_MODE, IOMUX1, 1<<5},
+ { RG_GPIO_LAN0_LED1_MODE, IOMUX1, 1<<4},
+ { RG_GPIO_LAN0_LED0_MODE, IOMUX1, 1<<3},
+ { RG_PON_TOD_1PPS_MODE, IOMUX1, 1<<2},
+ { RG_SW_TOD_1PPS_MODE, IOMUX1, 1<<1},
+ { RG_GPIO_2ND_I2C_MODE, IOMUX1, 1<<0},
+
+ // IOMUX Control 2 Register
+ { RG_GPIO_PCM_SPI_CS4_MODE, IOMUX2, 1<<21},
+ { RG_GPIO_PCM_SPI_CS3_MODE, IOMUX2, 1<<20},
+ { RG_GPIO_PCM_SPI_CS2_MODE_156PIN, IOMUX2, 1<<19},
+ { RG_GPIO_PCM_SPI_CS2_MODE_128PIN, IOMUX2, 1<<18},
+ { RG_GPIO_PCM_SPI_CS1_MODE, IOMUX2, 1<<17},
+ { RG_GPIO_PCM_SPI_MODE, IOMUX2, 1<<16},
+ { RG_GPIO_PCM2_MODE, IOMUX2, 1<<13},
+ { RG_GPIO_PCM1_MODE, IOMUX2, 1<<12},
+ { RG_GPIO_PCM_INT_MODE, IOMUX2, 1<<9},
+ { RG_GPIO_PCM_RESET_MODE, IOMUX2, 1<<8},
+ { RG_GPIO_SPI_QUAD_MODE, IOMUX2, 1<<4},
+ { RG_GPIO_SPI_CS1_MODE, IOMUX2, 1<<0},
+
+ // IOMUX Control 3 Register
+ { RG_GPIO_PARALLEL_NAND_MODE, IOMUX3, 1<<14},
+ { RG_GPIO_SGMII_MDIO_MODE, IOMUX3, 1<<13},
+ { RG_PCIE_RESET2_GPIO_MODE, IOMUX3, 1<<11},
+ { RG_SIPO_RCLK_MODE, IOMUX3, 1<<11},
+ { RG_PCIE_RESET1_GPIO_MODE, IOMUX3, 1<<10},
+ { RG_PCIE_RESET0_GPIO_MODE, IOMUX3, 1<<9},
+ { RG_GPIO_UART5_MODE, IOMUX3, 1<<8},
+ { RG_GPIO_UART4_MODE, IOMUX3, 1<<7},
+ { RG_GPIO_HSUART3_CTS_RTS_MODE, IOMUX3, 1<<6},
+ { RG_GPIO_HSUART3_MODE, IOMUX3, 1<<5},
+ { RG_GPIO_UART2_CTS_RTS_MODE, IOMUX3, 1<<4},
+ { RG_GPIO_UART2_MODE, IOMUX3, 1<<3},
+ { RG_SIPO_MODE, IOMUX3, 1<<2},
+ { RG_GPIO_EMMC_MODE, IOMUX3, 1<<1},
+ { RG_GPIO_PON_MODE, IOMUX3, 1<<0},
+
+ // IOMUX Control 5 Register
+ { RG_UDI_EJTAG_EN, IOMUX5, 1<<4},
+ { RG_DFD_EJTAG_EN, IOMUX5, 1<<3},
+ { RG_NPU_UART_EN, IOMUX5, 1<<2},
+
+ // IOMUX Control 6 Register
+ { RG_FORCE_GPIO31_EN, IOMUX6, 1<<31},
+ { RG_FORCE_GPIO30_EN, IOMUX6, 1<<30},
+ { RG_FORCE_GPIO29_EN, IOMUX6, 1<<29},
+ { RG_FORCE_GPIO28_EN, IOMUX6, 1<<28},
+ { RG_FORCE_GPIO27_EN, IOMUX6, 1<<27},
+ { RG_FORCE_GPIO26_EN, IOMUX6, 1<<26},
+ { RG_FORCE_GPIO25_EN, IOMUX6, 1<<25},
+ { RG_FORCE_GPIO24_EN, IOMUX6, 1<<24},
+ { RG_FORCE_GPIO23_EN, IOMUX6, 1<<23},
+ { RG_FORCE_GPIO22_EN, IOMUX6, 1<<22},
+ { RG_FORCE_GPIO21_EN, IOMUX6, 1<<21},
+ { RG_FORCE_GPIO20_EN, IOMUX6, 1<<20},
+ { RG_FORCE_GPIO19_EN, IOMUX6, 1<<19},
+ { RG_FORCE_GPIO18_EN, IOMUX6, 1<<18},
+ { RG_FORCE_GPIO17_EN, IOMUX6, 1<<17},
+ { RG_FORCE_GPIO16_EN, IOMUX6, 1<<16},
+ { RG_FORCE_GPIO15_EN, IOMUX6, 1<<15},
+ { RG_FORCE_GPIO14_EN, IOMUX6, 1<<14},
+ { RG_FORCE_GPIO13_EN, IOMUX6, 1<<13},
+ { RG_FORCE_GPIO12_EN, IOMUX6, 1<<12},
+ { RG_FORCE_GPIO11_EN, IOMUX6, 1<<11},
+ { RG_FORCE_GPIO10_EN, IOMUX6, 1<<10},
+ { RG_FORCE_GPIO9_EN, IOMUX6, 1<<9},
+ { RG_FORCE_GPIO8_EN, IOMUX6, 1<<8},
+ { RG_FORCE_GPIO7_EN, IOMUX6, 1<<7},
+ { RG_FORCE_GPIO6_EN, IOMUX6, 1<<6},
+ { RG_FORCE_GPIO5_EN, IOMUX6, 1<<5},
+ { RG_FORCE_GPIO4_EN, IOMUX6, 1<<4},
+ { RG_FORCE_GPIO3_EN, IOMUX6, 1<<3},
+ { RG_FORCE_GPIO2_EN, IOMUX6, 1<<2},
+ { RG_FORCE_GPIO1_EN, IOMUX6, 1<<1},
+
+ // IOMUX Control 7 Register
+ { RG_FORCE_GPIO46_EN, IOMUX7, 1<<14},
+ { RG_FORCE_GPIO45_EN, IOMUX7, 1<<13},
+ { RG_FORCE_GPIO44_EN, IOMUX7, 1<<12},
+ { RG_FORCE_GPIO43_EN, IOMUX7, 1<<11},
+ { RG_FORCE_GPIO42_EN, IOMUX7, 1<<10},
+ { RG_FORCE_GPIO41_EN, IOMUX7, 1<<9},
+ { RG_FORCE_GPIO40_EN, IOMUX7, 1<<8},
+ { RG_FORCE_GPIO39_EN, IOMUX7, 1<<7},
+ { RG_FORCE_GPIO38_EN, IOMUX7, 1<<6},
+ { RG_FORCE_GPIO37_EN, IOMUX7, 1<<5},
+ { RG_FORCE_GPIO36_EN, IOMUX7, 1<<4},
+ { RG_FORCE_GPIO35_EN, IOMUX7, 1<<3},
+ { RG_FORCE_GPIO34_EN, IOMUX7, 1<<2},
+ { RG_FORCE_GPIO33_EN, IOMUX7, 1<<1},
+ { RG_FORCE_GPIO32_EN, IOMUX7, 1<<0},
+
+ // IOMUX Reserve 1 Register
+ { RG_INIC_MDIO2OCP_MODE_SEL, IOMUX_RESERVE1, 1<<1},
+ { RG_INIC_MDIO_SLAVE_MODE, IOMUX_RESERVE1, 1<<0},
+
+ // LED0 Mapping Register
+ { RG_LAN3_LED0_MAPPING_LAN0, LED0_MAP, 0x0},
+ { RG_LAN3_LED0_MAPPING_LAN1, LED0_MAP, 0x1000},
+ { RG_LAN3_LED0_MAPPING_LAN2, LED0_MAP, 0x2000},
+ { RG_LAN3_LED0_MAPPING_LAN3, LED0_MAP, 0x3000},
+ { RG_LAN3_LED0_MAPPING_LAN4, LED0_MAP, 0x4000},
+ { RG_LAN2_LED0_MAPPING_LAN0, LED0_MAP, 0x0},
+ { RG_LAN2_LED0_MAPPING_LAN1, LED0_MAP, 0x100},
+ { RG_LAN2_LED0_MAPPING_LAN2, LED0_MAP, 0x200},
+ { RG_LAN2_LED0_MAPPING_LAN3, LED0_MAP, 0x300},
+ { RG_LAN2_LED0_MAPPING_LAN4, LED0_MAP, 0x400},
+ { RG_LAN1_LED0_MAPPING_LAN0, LED0_MAP, 0x0},
+ { RG_LAN1_LED0_MAPPING_LAN1, LED0_MAP, 0x10},
+ { RG_LAN1_LED0_MAPPING_LAN2, LED0_MAP, 0x20},
+ { RG_LAN1_LED0_MAPPING_LAN3, LED0_MAP, 0x30},
+ { RG_LAN1_LED0_MAPPING_LAN4, LED0_MAP, 0x40},
+ { RG_LAN0_LED0_MAPPING_LAN0, LED0_MAP, 0x0},
+ { RG_LAN0_LED0_MAPPING_LAN1, LED0_MAP, 0x1},
+ { RG_LAN0_LED0_MAPPING_LAN2, LED0_MAP, 0x2},
+ { RG_LAN0_LED0_MAPPING_LAN3, LED0_MAP, 0x3},
+ { RG_LAN0_LED0_MAPPING_LAN4, LED0_MAP, 0x4},
+
+ // LED1 Mapping Register
+ { RG_LAN3_LED1_MAPPING_LAN0, LED1_MAP, 0x0},
+ { RG_LAN3_LED1_MAPPING_LAN1, LED1_MAP, 0x1000},
+ { RG_LAN3_LED1_MAPPING_LAN2, LED1_MAP, 0x2000},
+ { RG_LAN3_LED1_MAPPING_LAN3, LED1_MAP, 0x3000},
+ { RG_LAN3_LED1_MAPPING_LAN4, LED1_MAP, 0x4000},
+ { RG_LAN2_LED1_MAPPING_LAN0, LED1_MAP, 0x0},
+ { RG_LAN2_LED1_MAPPING_LAN1, LED1_MAP, 0x100},
+ { RG_LAN2_LED1_MAPPING_LAN2, LED1_MAP, 0x200},
+ { RG_LAN2_LED1_MAPPING_LAN3, LED1_MAP, 0x300},
+ { RG_LAN2_LED1_MAPPING_LAN4, LED1_MAP, 0x400},
+ { RG_LAN1_LED1_MAPPING_LAN0, LED1_MAP, 0x0},
+ { RG_LAN1_LED1_MAPPING_LAN1, LED1_MAP, 0x10},
+ { RG_LAN1_LED1_MAPPING_LAN2, LED1_MAP, 0x20},
+ { RG_LAN1_LED1_MAPPING_LAN3, LED1_MAP, 0x30},
+ { RG_LAN1_LED1_MAPPING_LAN4, LED1_MAP, 0x40},
+ { RG_LAN0_LED1_MAPPING_LAN0, LED1_MAP, 0x0},
+ { RG_LAN0_LED1_MAPPING_LAN1, LED1_MAP, 0x1},
+ { RG_LAN0_LED1_MAPPING_LAN2, LED1_MAP, 0x2},
+ { RG_LAN0_LED1_MAPPING_LAN3, LED1_MAP, 0x3},
+ { RG_LAN0_LED1_MAPPING_LAN4, LED1_MAP, 0x4},
+
+ // IO TX Driving Control 1
+ { RG_SPI_MISO_E2, IO_DRIVE_CTRL1, 1<<13},
+ { RG_SPI_MOSI_E2, IO_DRIVE_CTRL1, 1<<12},
+ { RG_SPI_CLK_E2, IO_DRIVE_CTRL1, 1<<11},
+ { RG_SPI_CS0_E2, IO_DRIVE_CTRL1, 1<<10},
+ { RG_PCIE1_RESET_E2, IO_DRIVE_CTRL1, 1<<9},
+ { RG_PCIE0_RESET_E2, IO_DRIVE_CTRL1, 1<<8},
+ { RG_UART1_RXD_E2, IO_DRIVE_CTRL1, 1<<3},
+ { RG_UART1_TXD_E2, IO_DRIVE_CTRL1, 1<<2},
+ { RG_I2C_SCL_E2, IO_DRIVE_CTRL1, 1<<1},
+ { RG_I2C_SDA_E2, IO_DRIVE_CTRL1, 1<<0},
+
+ // IO TX Driving Control 2
+ { RG_SPI_MISO_E4, IO_DRIVE_CTRL2, 1<<13},
+ { RG_SPI_MOSI_E4, IO_DRIVE_CTRL2, 1<<12},
+ { RG_SPI_CLK_E4, IO_DRIVE_CTRL2, 1<<11},
+ { RG_SPI_CS0_E4, IO_DRIVE_CTRL2, 1<<10},
+ { RG_PCIE1_RESET_E4, IO_DRIVE_CTRL2, 1<<9},
+ { RG_PCIE0_RESET_E4, IO_DRIVE_CTRL2, 1<<8},
+ { RG_UART1_RXD_E4, IO_DRIVE_CTRL2, 1<<3},
+ { RG_UART1_TXD_E4, IO_DRIVE_CTRL2, 1<<2},
+ { RG_I2C_SCL_E4, IO_DRIVE_CTRL2, 1<<1},
+ { RG_I2C_SDA_E4, IO_DRIVE_CTRL2, 1<<0},
+
+ // GPIO lower byte TX Driving Control 1
+ { RG_GPIO0_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<0},
+ { RG_GPIO1_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<1},
+ { RG_GPIO2_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<2},
+ { RG_GPIO3_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<3},
+ { RG_GPIO4_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<4},
+ { RG_GPIO5_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<5},
+ { RG_GPIO6_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<6},
+ { RG_GPIO7_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<7},
+ { RG_GPIO8_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<8},
+ { RG_GPIO9_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<9},
+ { RG_GPIO10_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<10},
+ { RG_GPIO11_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<11},
+ { RG_GPIO12_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<12},
+ { RG_GPIO13_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<13},
+ { RG_GPIO14_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<14},
+ { RG_GPIO15_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<15},
+ { RG_GPIO16_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<16},
+ { RG_GPIO17_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<17},
+ { RG_GPIO18_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<18},
+ { RG_GPIO19_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<19},
+ { RG_GPIO20_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<20},
+ { RG_GPIO21_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<21},
+ { RG_GPIO22_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<22},
+ { RG_GPIO23_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<23},
+ { RG_GPIO24_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<24},
+ { RG_GPIO25_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<25},
+ { RG_GPIO26_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<26},
+ { RG_GPIO27_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<27},
+ { RG_GPIO28_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<28},
+ { RG_GPIO29_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<29},
+ { RG_GPIO30_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<30},
+ { RG_GPIO31_L_E2, GPIO_LB_DRIVE_CTRL1, 1<<31},
+
+ // GPIO lower byte TX Driving Control 2
+ { RG_GPIO0_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<0},
+ { RG_GPIO1_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<1},
+ { RG_GPIO2_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<2},
+ { RG_GPIO3_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<3},
+ { RG_GPIO4_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<4},
+ { RG_GPIO5_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<5},
+ { RG_GPIO6_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<6},
+ { RG_GPIO7_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<7},
+ { RG_GPIO8_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<8},
+ { RG_GPIO9_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<9},
+ { RG_GPIO10_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<10},
+ { RG_GPIO11_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<11},
+ { RG_GPIO12_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<12},
+ { RG_GPIO13_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<13},
+ { RG_GPIO14_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<14},
+ { RG_GPIO15_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<15},
+ { RG_GPIO16_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<16},
+ { RG_GPIO17_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<17},
+ { RG_GPIO18_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<18},
+ { RG_GPIO19_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<19},
+ { RG_GPIO20_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<20},
+ { RG_GPIO21_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<21},
+ { RG_GPIO22_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<22},
+ { RG_GPIO23_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<23},
+ { RG_GPIO24_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<24},
+ { RG_GPIO25_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<25},
+ { RG_GPIO26_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<26},
+ { RG_GPIO27_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<27},
+ { RG_GPIO28_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<28},
+ { RG_GPIO29_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<29},
+ { RG_GPIO30_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<30},
+ { RG_GPIO31_L_E4, GPIO_LB_DRIVE_CTRL2, 1<<31},
+
+ // GPIO higher byte TX Driving Control 1
+ { RG_GPIO32_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<0},
+ { RG_GPIO33_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<1},
+ { RG_GPIO34_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<2},
+ { RG_GPIO35_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<3},
+ { RG_GPIO36_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<4},
+ { RG_GPIO37_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<5},
+ { RG_GPIO38_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<6},
+ { RG_GPIO39_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<7},
+ { RG_GPIO40_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<8},
+ { RG_GPIO41_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<9},
+ { RG_GPIO42_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<10},
+ { RG_GPIO43_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<11},
+ { RG_GPIO44_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<12},
+ { RG_GPIO45_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<13},
+ { RG_GPIO46_H_E2, GPIO_HB_DRIVE_CTRL1, 1<<14},
+
+ // GPIO higher byte TX Driving Control 2
+ { RG_GPIO32_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<0},
+ { RG_GPIO33_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<1},
+ { RG_GPIO34_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<2},
+ { RG_GPIO35_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<3},
+ { RG_GPIO36_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<4},
+ { RG_GPIO37_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<5},
+ { RG_GPIO38_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<6},
+ { RG_GPIO39_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<7},
+ { RG_GPIO40_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<8},
+ { RG_GPIO41_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<9},
+ { RG_GPIO42_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<10},
+ { RG_GPIO43_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<11},
+ { RG_GPIO44_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<12},
+ { RG_GPIO45_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<13},
+ { RG_GPIO46_H_E4, GPIO_HB_DRIVE_CTRL2, 1<<14},
+
+ // IO Pull Up Control 1
+ { RG_SPI_MISO_PU, IO_PULL_UP_CTRL1, 1<<14},
+ { RG_SPI_MOSI_PU, IO_PULL_UP_CTRL1, 1<<13},
+ { RG_SPI_CLK_PU, IO_PULL_UP_CTRL1, 1<<12},
+ { RG_SPI_CS0_PU, IO_PULL_UP_CTRL1, 1<<11},
+ { RG_PCIE2_RESET_PU, IO_PULL_UP_CTRL1, 1<<10},
+ { RG_PCIE1_RESET_PU, IO_PULL_UP_CTRL1, 1<<9},
+ { RG_PCIE0_RESET_PU, IO_PULL_UP_CTRL1, 1<<8},
+ { RG_UART1_RXD_PU, IO_PULL_UP_CTRL1, 1<<3},
+ { RG_UART1_TXD_PU, IO_PULL_UP_CTRL1, 1<<2},
+ { RG_I2C_SCL_PU, IO_PULL_UP_CTRL1, 1<<1},
+ { RG_I2C_SDA_PU, IO_PULL_UP_CTRL1, 1<<0},
+
+ // IO Pull Down Control 2
+ { RG_SPI_MISO_PD, IO_PULL_DOWN_CTRL2, 1<<14},
+ { RG_SPI_MOSI_PD, IO_PULL_DOWN_CTRL2, 1<<13},
+ { RG_SPI_CLK_PD, IO_PULL_DOWN_CTRL2, 1<<12},
+ { RG_SPI_CS0_PD, IO_PULL_DOWN_CTRL2, 1<<11},
+ { RG_PCIE2_RESET_PD, IO_PULL_DOWN_CTRL2, 1<<10},
+ { RG_PCIE1_RESET_PD, IO_PULL_DOWN_CTRL2, 1<<9},
+ { RG_PCIE0_RESET_PD, IO_PULL_DOWN_CTRL2, 1<<8},
+ { RG_UART1_RXD_PD, IO_PULL_DOWN_CTRL2, 1<<3},
+ { RG_UART1_TXD_PD, IO_PULL_DOWN_CTRL2, 1<<2},
+ { RG_I2C_SCL_PD, IO_PULL_DOWN_CTRL2, 1<<1},
+ { RG_I2C_SDA_PD, IO_PULL_DOWN_CTRL2, 1<<0},
+
+ // GPIO lower byte Pull Up Control
+ { RG_GPIO0_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<0},
+ { RG_GPIO1_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<1},
+ { RG_GPIO2_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<2},
+ { RG_GPIO3_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<3},
+ { RG_GPIO4_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<4},
+ { RG_GPIO5_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<5},
+ { RG_GPIO6_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<6},
+ { RG_GPIO7_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<7},
+ { RG_GPIO8_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<8},
+ { RG_GPIO9_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<9},
+ { RG_GPIO10_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<10},
+ { RG_GPIO11_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<11},
+ { RG_GPIO12_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<12},
+ { RG_GPIO13_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<13},
+ { RG_GPIO14_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<14},
+ { RG_GPIO15_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<15},
+ { RG_GPIO16_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<16},
+ { RG_GPIO17_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<17},
+ { RG_GPIO18_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<18},
+ { RG_GPIO19_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<19},
+ { RG_GPIO20_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<20},
+ { RG_GPIO21_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<21},
+ { RG_GPIO22_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<22},
+ { RG_GPIO23_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<23},
+ { RG_GPIO24_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<24},
+ { RG_GPIO25_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<25},
+ { RG_GPIO26_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<26},
+ { RG_GPIO27_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<27},
+ { RG_GPIO28_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<28},
+ { RG_GPIO29_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<29},
+ { RG_GPIO30_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<30},
+ { RG_GPIO31_L_PU, GPIO_LB_PULL_UP_CTRL, 1<<31},
+
+ // GPIO lower byte Pull Down Control
+ { RG_GPIO0_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<0},
+ { RG_GPIO1_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<1},
+ { RG_GPIO2_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<2},
+ { RG_GPIO3_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<3},
+ { RG_GPIO4_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<4},
+ { RG_GPIO5_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<5},
+ { RG_GPIO6_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<6},
+ { RG_GPIO7_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<7},
+ { RG_GPIO8_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<8},
+ { RG_GPIO9_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<9},
+ { RG_GPIO10_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<10},
+ { RG_GPIO11_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<11},
+ { RG_GPIO12_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<12},
+ { RG_GPIO13_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<13},
+ { RG_GPIO14_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<14},
+ { RG_GPIO15_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<15},
+ { RG_GPIO16_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<16},
+ { RG_GPIO17_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<17},
+ { RG_GPIO18_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<18},
+ { RG_GPIO19_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<19},
+ { RG_GPIO20_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<20},
+ { RG_GPIO21_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<21},
+ { RG_GPIO22_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<22},
+ { RG_GPIO23_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<23},
+ { RG_GPIO24_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<24},
+ { RG_GPIO25_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<25},
+ { RG_GPIO26_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<26},
+ { RG_GPIO27_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<27},
+ { RG_GPIO28_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<28},
+ { RG_GPIO29_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<29},
+ { RG_GPIO30_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<30},
+ { RG_GPIO31_L_PD, GPIO_LB_PULL_DOWN_CTRL, 1<<31},
+
+ // GPIO higher byte Pull Up Control
+ { RG_GPIO32_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<0},
+ { RG_GPIO33_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<1},
+ { RG_GPIO34_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<2},
+ { RG_GPIO35_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<3},
+ { RG_GPIO36_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<4},
+ { RG_GPIO37_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<5},
+ { RG_GPIO38_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<6},
+ { RG_GPIO39_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<7},
+ { RG_GPIO40_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<8},
+ { RG_GPIO41_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<9},
+ { RG_GPIO42_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<10},
+ { RG_GPIO43_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<11},
+ { RG_GPIO44_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<12},
+ { RG_GPIO45_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<13},
+ { RG_GPIO46_H_PU, GPIO_HB_PULL_UP_CTRL, 1<<14},
+
+ // GPIO higher byte Pull Down Control
+ { RG_GPIO32_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<0},
+ { RG_GPIO33_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<1},
+ { RG_GPIO34_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<2},
+ { RG_GPIO35_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<3},
+ { RG_GPIO36_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<4},
+ { RG_GPIO37_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<5},
+ { RG_GPIO38_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<6},
+ { RG_GPIO39_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<7},
+ { RG_GPIO40_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<8},
+ { RG_GPIO41_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<9},
+ { RG_GPIO42_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<10},
+ { RG_GPIO43_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<11},
+ { RG_GPIO44_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<12},
+ { RG_GPIO45_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<13},
+ { RG_GPIO46_H_PD, GPIO_HB_PULL_DOWN_CTRL, 1<<14},
+};
+
+static struct pinctrl_pin_desc an7581_pins[] = {
+ PINCTRL_PIN(1, "UART1_TXD"),
+ PINCTRL_PIN(2, "UART1_RXD"),
+ PINCTRL_PIN(3, "I2C_SCL"),
+ PINCTRL_PIN(4, "I2C_SDA"),
+ PINCTRL_PIN(5, "SPI_CS0"),
+ PINCTRL_PIN(6, "SPI_CLK"),
+ PINCTRL_PIN(7, "SPI_MOSI"),
+ PINCTRL_PIN(8, "SPI_MISO"),
+ PINCTRL_PIN(9, "HW_RSTN"),
+ PINCTRL_PIN(10, "PKG_SEL0"),
+ PINCTRL_PIN(11, "PKG_SEL1"),
+ PINCTRL_PIN(12, "PKG_SEL2"),
+ PINCTRL_PIN(13, "PKG_SEL3"),
+ PINCTRL_PIN(14, "GPIO0"),
+ PINCTRL_PIN(15, "GPIO1"),
+ PINCTRL_PIN(16, "GPIO2"),
+ PINCTRL_PIN(17, "GPIO3"),
+ PINCTRL_PIN(18, "GPIO4"),
+ PINCTRL_PIN(19, "GPIO5"),
+ PINCTRL_PIN(20, "GPIO6"),
+ PINCTRL_PIN(21, "GPIO7"),
+ PINCTRL_PIN(22, "GPIO8"),
+ PINCTRL_PIN(23, "GPIO9"),
+ PINCTRL_PIN(24, "GPIO10"),
+ PINCTRL_PIN(25, "GPIO11"),
+ PINCTRL_PIN(26, "GPIO12"),
+ PINCTRL_PIN(27, "GPIO13"),
+ PINCTRL_PIN(28, "GPIO14"),
+ PINCTRL_PIN(29, "GPIO15"),
+ PINCTRL_PIN(30, "GPIO16"),
+ PINCTRL_PIN(31, "GPIO17"),
+ PINCTRL_PIN(32, "GPIO18"),
+ PINCTRL_PIN(33, "GPIO19"),
+ PINCTRL_PIN(34, "GPIO20"),
+ PINCTRL_PIN(35, "GPIO21"),
+ PINCTRL_PIN(36, "GPIO22"),
+ PINCTRL_PIN(37, "GPIO23"),
+ PINCTRL_PIN(38, "GPIO24"),
+ PINCTRL_PIN(39, "GPIO25"),
+ PINCTRL_PIN(40, "GPIO26"),
+ PINCTRL_PIN(41, "GPIO27"),
+ PINCTRL_PIN(42, "GPIO28"),
+ PINCTRL_PIN(43, "GPIO29"),
+ PINCTRL_PIN(44, "GPIO30"),
+ PINCTRL_PIN(45, "GPIO31"),
+ PINCTRL_PIN(46, "GPIO32"),
+ PINCTRL_PIN(47, "GPIO33"),
+ PINCTRL_PIN(48, "GPIO34"),
+ PINCTRL_PIN(49, "GPIO35"),
+ PINCTRL_PIN(50, "GPIO36"),
+ PINCTRL_PIN(51, "GPIO37"),
+ PINCTRL_PIN(52, "GPIO38"),
+ PINCTRL_PIN(53, "GPIO39"),
+ PINCTRL_PIN(54, "GPIO40"),
+ PINCTRL_PIN(55, "GPIO41"),
+ PINCTRL_PIN(56, "GPIO42"),
+ PINCTRL_PIN(57, "GPIO43"),
+ PINCTRL_PIN(58, "GPIO44"),
+ PINCTRL_PIN(59, "GPIO45"),
+ PINCTRL_PIN(60, "GPIO46"),
+ // No 61
+ PINCTRL_PIN(62, "PCIE_RESET0_SW"),
+ PINCTRL_PIN(63, "PCIE_RESET1_SW"),
+ PINCTRL_PIN(64, "PCIE_RESET2_SW"),
+ PINCTRL_PIN(65, "MDC_0"),
+ PINCTRL_PIN(66, "MDIO_0"),
+};
+
+static struct an7581_pin_setting an7581_pin_settings[] = {
+ { 1, RG_UART1_TXD_PU, RG_UART1_TXD_PD, RG_UART1_TXD_E2, RG_UART1_TXD_E4, RG_REG_NULL },
+ { 2, RG_UART1_RXD_PU, RG_UART1_RXD_PD, RG_UART1_RXD_E2, RG_UART1_RXD_E4, RG_REG_NULL },
+ { 3, RG_I2C_SDA_PU, RG_I2C_SDA_PD, RG_I2C_SDA_E2, RG_I2C_SDA_E4, RG_REG_NULL },
+ { 4, RG_I2C_SCL_PU, RG_I2C_SCL_PD, RG_I2C_SCL_E2, RG_I2C_SCL_E4, RG_REG_NULL },
+ { 5, RG_SPI_CS0_PU, RG_SPI_CS0_PD, RG_SPI_CS0_E2, RG_SPI_CS0_E4, RG_REG_NULL },
+ { 6, RG_SPI_CLK_PU, RG_SPI_CLK_PD, RG_SPI_CS0_E2, RG_SPI_CLK_E4, RG_REG_NULL },
+ { 7, RG_SPI_MOSI_PU, RG_SPI_MOSI_PD, RG_SPI_MOSI_E2, RG_SPI_MOSI_E4, RG_REG_NULL },
+ { 8, RG_SPI_MISO_PU, RG_SPI_MISO_PD, RG_SPI_MISO_E2, RG_SPI_MISO_E4, RG_REG_NULL },
+ { 9, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL },
+ { 10, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL },
+ { 11, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL },
+ { 12, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL },
+ { 13, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL, RG_REG_NULL },
+ { 14, RG_GPIO0_L_PU, RG_GPIO0_L_PD, RG_GPIO0_L_E2, RG_GPIO0_L_E4, RG_REG_NULL },
+ { 15, RG_GPIO1_L_PU, RG_GPIO1_L_PD, RG_GPIO1_L_E2, RG_GPIO1_L_E4, RG_FORCE_GPIO1_EN },
+ { 16, RG_GPIO2_L_PU, RG_GPIO2_L_PD, RG_GPIO2_L_E2, RG_GPIO2_L_E4, RG_FORCE_GPIO2_EN },
+ { 17, RG_GPIO3_L_PU, RG_GPIO3_L_PD, RG_GPIO3_L_E2, RG_GPIO3_L_E4, RG_FORCE_GPIO3_EN },
+ { 18, RG_GPIO4_L_PU, RG_GPIO4_L_PD, RG_GPIO4_L_E2, RG_GPIO4_L_E4, RG_FORCE_GPIO4_EN },
+ { 19, RG_GPIO5_L_PU, RG_GPIO5_L_PD, RG_GPIO5_L_E2, RG_GPIO5_L_E4, RG_FORCE_GPIO5_EN },
+ { 10, RG_GPIO6_L_PU, RG_GPIO6_L_PD, RG_GPIO6_L_E2, RG_GPIO6_L_E4, RG_FORCE_GPIO6_EN },
+ { 11, RG_GPIO7_L_PU, RG_GPIO7_L_PD, RG_GPIO7_L_E2, RG_GPIO7_L_E4, RG_FORCE_GPIO7_EN },
+ { 22, RG_GPIO8_L_PU, RG_GPIO8_L_PD, RG_GPIO8_L_E2, RG_GPIO8_L_E4, RG_FORCE_GPIO8_EN },
+ { 23, RG_GPIO9_L_PU, RG_GPIO9_L_PD, RG_GPIO9_L_E2, RG_GPIO9_L_E4, RG_FORCE_GPIO9_EN },
+ { 24, RG_GPIO10_L_PU, RG_GPIO10_L_PD, RG_GPIO10_L_E2, RG_GPIO10_L_E4, RG_FORCE_GPIO10_EN },
+ { 25, RG_GPIO11_L_PU, RG_GPIO11_L_PD, RG_GPIO11_L_E2, RG_GPIO11_L_E4, RG_FORCE_GPIO11_EN },
+ { 26, RG_GPIO12_L_PU, RG_GPIO12_L_PD, RG_GPIO12_L_E2, RG_GPIO12_L_E4, RG_FORCE_GPIO12_EN },
+ { 27, RG_GPIO13_L_PU, RG_GPIO13_L_PD, RG_GPIO13_L_E2, RG_GPIO13_L_E4, RG_FORCE_GPIO13_EN },
+ { 28, RG_GPIO14_L_PU, RG_GPIO14_L_PD, RG_GPIO14_L_E2, RG_GPIO14_L_E4, RG_FORCE_GPIO14_EN },
+ { 29, RG_GPIO15_L_PU, RG_GPIO15_L_PD, RG_GPIO15_L_E2, RG_GPIO15_L_E4, RG_FORCE_GPIO15_EN },
+ { 30, RG_GPIO16_L_PU, RG_GPIO16_L_PD, RG_GPIO16_L_E2, RG_GPIO16_L_E4, RG_FORCE_GPIO16_EN },
+ { 31, RG_GPIO17_L_PU, RG_GPIO17_L_PD, RG_GPIO17_L_E2, RG_GPIO17_L_E4, RG_FORCE_GPIO17_EN },
+ { 32, RG_GPIO18_L_PU, RG_GPIO18_L_PD, RG_GPIO18_L_E2, RG_GPIO18_L_E4, RG_FORCE_GPIO18_EN },
+ { 33, RG_GPIO19_L_PU, RG_GPIO19_L_PD, RG_GPIO19_L_E2, RG_GPIO19_L_E4, RG_FORCE_GPIO19_EN },
+ { 34, RG_GPIO20_L_PU, RG_GPIO20_L_PD, RG_GPIO20_L_E2, RG_GPIO20_L_E4, RG_FORCE_GPIO20_EN },
+ { 35, RG_GPIO21_L_PU, RG_GPIO21_L_PD, RG_GPIO21_L_E2, RG_GPIO21_L_E4, RG_FORCE_GPIO21_EN },
+ { 36, RG_GPIO22_L_PU, RG_GPIO22_L_PD, RG_GPIO22_L_E2, RG_GPIO22_L_E4, RG_FORCE_GPIO22_EN },
+ { 37, RG_GPIO23_L_PU, RG_GPIO23_L_PD, RG_GPIO23_L_E2, RG_GPIO23_L_E4, RG_FORCE_GPIO23_EN },
+ { 38, RG_GPIO24_L_PU, RG_GPIO24_L_PD, RG_GPIO24_L_E2, RG_GPIO24_L_E4, RG_FORCE_GPIO24_EN },
+ { 39, RG_GPIO25_L_PU, RG_GPIO25_L_PD, RG_GPIO25_L_E2, RG_GPIO25_L_E4, RG_FORCE_GPIO25_EN },
+ { 40, RG_GPIO26_L_PU, RG_GPIO26_L_PD, RG_GPIO26_L_E2, RG_GPIO26_L_E4, RG_FORCE_GPIO26_EN },
+ { 41, RG_GPIO27_L_PU, RG_GPIO27_L_PD, RG_GPIO27_L_E2, RG_GPIO27_L_E4, RG_FORCE_GPIO27_EN },
+ { 42, RG_GPIO28_L_PU, RG_GPIO28_L_PD, RG_GPIO28_L_E2, RG_GPIO28_L_E4, RG_FORCE_GPIO28_EN },
+ { 43, RG_GPIO29_L_PU, RG_GPIO29_L_PD, RG_GPIO29_L_E2, RG_GPIO29_L_E4, RG_FORCE_GPIO29_EN },
+ { 44, RG_GPIO30_L_PU, RG_GPIO30_L_PD, RG_GPIO30_L_E2, RG_GPIO30_L_E4, RG_FORCE_GPIO30_EN },
+ { 45, RG_GPIO31_L_PU, RG_GPIO31_L_PD, RG_GPIO31_L_E2, RG_GPIO31_L_E4, RG_FORCE_GPIO31_EN },
+ { 46, RG_GPIO32_H_PU, RG_GPIO32_H_PD, RG_GPIO32_H_E2, RG_GPIO32_H_E4, RG_FORCE_GPIO32_EN },
+ { 47, RG_GPIO33_H_PU, RG_GPIO33_H_PD, RG_GPIO33_H_E2, RG_GPIO33_H_E4, RG_FORCE_GPIO33_EN },
+ { 48, RG_GPIO34_H_PU, RG_GPIO34_H_PD, RG_GPIO34_H_E2, RG_GPIO34_H_E4, RG_FORCE_GPIO34_EN },
+ { 49, RG_GPIO35_H_PU, RG_GPIO35_H_PD, RG_GPIO35_H_E2, RG_GPIO35_H_E4, RG_FORCE_GPIO35_EN },
+ { 50, RG_GPIO36_H_PU, RG_GPIO36_H_PD, RG_GPIO36_H_E2, RG_GPIO36_H_E4, RG_FORCE_GPIO36_EN },
+ { 51, RG_GPIO37_H_PU, RG_GPIO37_H_PD, RG_GPIO37_H_E2, RG_GPIO37_H_E4, RG_FORCE_GPIO37_EN },
+ { 52, RG_GPIO38_H_PU, RG_GPIO38_H_PD, RG_GPIO38_H_E2, RG_GPIO38_H_E4, RG_FORCE_GPIO38_EN },
+ { 53, RG_GPIO39_H_PU, RG_GPIO39_H_PD, RG_GPIO39_H_E2, RG_GPIO39_H_E4, RG_FORCE_GPIO39_EN },
+ { 54, RG_GPIO40_H_PU, RG_GPIO40_H_PD, RG_GPIO40_H_E2, RG_GPIO40_H_E4, RG_FORCE_GPIO40_EN },
+ { 55, RG_GPIO41_H_PU, RG_GPIO41_H_PD, RG_GPIO41_H_E2, RG_GPIO41_H_E4, RG_FORCE_GPIO41_EN },
+ { 56, RG_GPIO42_H_PU, RG_GPIO42_H_PD, RG_GPIO42_H_E2, RG_GPIO42_H_E4, RG_FORCE_GPIO42_EN },
+ { 57, RG_GPIO43_H_PU, RG_GPIO43_H_PD, RG_GPIO43_H_E2, RG_GPIO43_H_E4, RG_FORCE_GPIO43_EN },
+ { 58, RG_GPIO44_H_PU, RG_GPIO44_H_PD, RG_GPIO44_H_E2, RG_GPIO44_H_E4, RG_FORCE_GPIO44_EN },
+ { 59, RG_GPIO45_H_PU, RG_GPIO45_H_PD, RG_GPIO45_H_E2, RG_GPIO45_H_E4, RG_FORCE_GPIO45_EN },
+ { 60, RG_GPIO46_H_PU, RG_GPIO46_H_PD, RG_GPIO46_H_E2, RG_GPIO46_H_E4, RG_FORCE_GPIO46_EN },
+ { 61, RG_PCIE0_RESET_PU, RG_PCIE0_RESET_PD, RG_PCIE0_RESET_E2, RG_PCIE0_RESET_E4, RG_PCIE_RESET0_GPIO_MODE },
+ { 62, RG_PCIE1_RESET_PU, RG_PCIE1_RESET_PD, RG_PCIE1_RESET_E2, RG_PCIE1_RESET_E4, RG_PCIE_RESET1_GPIO_MODE },
+ { 63, RG_PCIE2_RESET_PU, RG_PCIE2_RESET_PD, RG_PCIE2_RESET_E2, RG_PCIE2_RESET_E4, RG_PCIE_RESET2_GPIO_MODE },
+};
+
+static const int pon_pins0[] = { 50, 51, 52, 53, 54, 55 };
+static const int tod_pins0[] = { 47 };
+static const int lan3_led1_pins0[] = { 60 };
+static const int lan2_led1_pins0[] = { 59 };
+static const int lan1_led1_pins0[] = { 58 };
+static const int lan0_led1_pins0[] = { 57 };
+static const int lan3_led0_pins0[] = { 56 };
+static const int lan2_led0_pins0[] = { 49 };
+static const int lan1_led0_pins0[] = { 48 };
+static const int lan0_led0_pins0[] = { 47 };
+static const int sipo_pins0[] = { 17, 18 };
+static const int sipo_rclk_pins1[] = { 17, 18, 44 };
+static const int i2c1_pins0[] = { 15, 16 };
+static const int sgmii_mdio_pins0[] = { 15, 16 };
+static const int uart2_pins0[] = { 49, 56 };
+static const int uart2_cts_rts_pins0[] = { 47, 48 };
+static const int hsuart3_pins0[] = { 29, 30 };
+static const int hsuart3_cts_rts_pins0[] = { 27, 28 };
+static const int uart4_pins0[] = { 39, 40 };
+static const int uart5_pins0[] = { 19, 20 };
+//static const int npu_uart_pins0[] = { }; maybe in one of the uart pins
+static const int jtag_udi_pins0[] = { 17, 18, 19, 20, 21 };
+static const int jtag_dfd_pins0[] = { 17, 18, 19, 20, 21 };
+static const int gpio_47_pins0[] = { 62 };
+static const int gpio_48_pins0[] = { 63 };
+static const int gpio_49_pins0[] = { 64 };
+static const int i2s0_pins0[] = { 27, 28, 29, 30 };
+static const int pcm1_pins0[] = { 23, 24, 25, 26 };
+static const int pcm2_pins0[] = { 19, 20, 21, 22 };
+static const int spi0_quad_pins0[] = { 33, 34 };
+static const int spi0_cs1_pins0[] = { 35 };
+static const int pcm_spi1_cs1_pins0[] = { 44 };
+static const int pcm_spi1_cs2_156_pins0[] = { 41 };
+static const int pcm_spi1_cs2_128_pins0[] = { 41 };
+static const int pcm_spi1_cs3_pins0[] = { 42 };
+static const int pcm_spi1_cs4_pins0[] = { 23 };
+static const int pcm_spi1_pins0[] = { 19, 20, 21, 22, 23, 24, 25, 26 };
+static const int pcm_spi0_pins0[] = { 19, 20, 21, 22, 23, 24, 25, 26 };
+static const int pcm_spi1_int_pins0[] = { 15 };
+static const int pcm_spi1_reset_pins0[] = { 16 };
+static const int emmc_pins0[] = { 5, 6, 7, 31, 32, 33, 34, 35, 36, 37, 38 };
+static const int parallel_nand_pins0[] = { 5, 6, 7, 8, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43 };
+
+static const struct an7581_pin_group an7581_pin_groups[] = {
+ {
+ .name = "pon0_grp",
+ .pins = pon_pins0,
+ .num_pins = ARRAY_SIZE(pon_pins0),
+ },
+ {
+ .name = "tod_pon_grp",
+ .pins = tod_pins0,
+ .num_pins = ARRAY_SIZE(tod_pins0),
+ },
+ {
+ .name = "tod_sw_grp",
+ .pins = tod_pins0,
+ .num_pins = ARRAY_SIZE(tod_pins0),
+ },
+ {
+ .name = "sipo_grp",
+ .pins = sipo_pins0,
+ .num_pins = ARRAY_SIZE(sipo_pins0),
+ },
+ {
+ .name = "sipo_rclk_grp",
+ .pins = sipo_rclk_pins1,
+ .num_pins = ARRAY_SIZE(sipo_rclk_pins1),
+ },
+ {
+ .name = "mdio_grp",
+ .pins = sgmii_mdio_pins0,
+ .num_pins = ARRAY_SIZE(sgmii_mdio_pins0),
+ },
+ {
+ .name = "uart2_grp",
+ .pins = uart2_pins0,
+ .num_pins = ARRAY_SIZE(uart2_pins0),
+ },
+ {
+ .name = "suart2_cts_rts_grp",
+ .pins = uart2_cts_rts_pins0,
+ .num_pins = ARRAY_SIZE(uart2_pins0),
+ },
+ {
+ .name = "hsuart3_grp",
+ .pins = hsuart3_pins0,
+ .num_pins = ARRAY_SIZE(hsuart3_pins0),
+ },
+ {
+ .name = "hsuart3_cts_rts_grp",
+ .pins = hsuart3_cts_rts_pins0,
+ .num_pins = ARRAY_SIZE(hsuart3_pins0),
+ },
+ {
+ .name = "uart4_grp",
+ .pins = uart4_pins0,
+ .num_pins = ARRAY_SIZE(uart4_pins0),
+ },
+ {
+ .name = "uart5_grp",
+ .pins = uart5_pins0,
+ .num_pins = ARRAY_SIZE(uart5_pins0),
+ },
+// {
+// .name = "npu_uart_grp",
+// .pins = npu_uart_pins0,
+// .num_pins = ARRAY_SIZE(npu_uart_pins0),
+// },
+ {
+ .name = "i2c1_grp",
+ .pins = i2c1_pins0,
+ .num_pins = ARRAY_SIZE(i2c1_pins0),
+ },
+ {
+ .name = "jtag_udi_grp",
+ .pins = jtag_udi_pins0,
+ .num_pins = ARRAY_SIZE(jtag_udi_pins0),
+ },
+ {
+ .name = "jtag_dfd_grp",
+ .pins = jtag_dfd_pins0,
+ .num_pins = ARRAY_SIZE(jtag_dfd_pins0),
+ },
+ {
+ .name = "gpio_47_grp",
+ .pins = gpio_47_pins0,
+ .num_pins = ARRAY_SIZE(gpio_47_pins0),
+ },
+ {
+ .name = "gpio_48_grp",
+ .pins = gpio_48_pins0,
+ .num_pins = ARRAY_SIZE(gpio_48_pins0),
+ },
+ {
+ .name = "gpio_49_grp",
+ .pins = gpio_49_pins0,
+ .num_pins = ARRAY_SIZE(gpio_49_pins0),
+ },
+ {
+ .name = "i2s_grp",
+ .pins = i2s0_pins0,
+ .num_pins = ARRAY_SIZE(i2s0_pins0),
+ },
+ {
+ .name = "pcm1_grp",
+ .pins = pcm1_pins0,
+ .num_pins = ARRAY_SIZE(pcm1_pins0),
+ },
+ {
+ .name = "pcm2_grp",
+ .pins = pcm2_pins0,
+ .num_pins = ARRAY_SIZE(pcm2_pins0),
+ },
+ {
+ .name = "spi0_quad_grp",
+ .pins = spi0_quad_pins0,
+ .num_pins = ARRAY_SIZE(spi0_quad_pins0),
+ },
+ {
+ .name = "spi0_cs1_grp",
+ .pins = spi0_cs1_pins0,
+ .num_pins = ARRAY_SIZE(spi0_cs1_pins0),
+ },
+ {
+ .name = "pcm_spi1_grp",
+ .pins = pcm_spi1_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_pins0),
+ },
+ {
+ .name = "pcm_spi0_grp",
+ .pins = pcm_spi1_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_pins0),
+ },
+ {
+ .name = "pcm_spi1_int_grp",
+ .pins = pcm_spi1_int_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_int_pins0),
+ },
+ {
+ .name = "pcm_spi1_reset_grp",
+ .pins = pcm_spi1_int_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_int_pins0),
+ },
+ {
+ .name = "pcm_spi1_cs1_grp",
+ .pins = pcm_spi1_cs1_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_cs1_pins0),
+ },
+ {
+ .name = "pcm_spi1_cs2_156_grp",
+ .pins = pcm_spi1_cs2_156_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_cs2_156_pins0),
+ },
+ {
+ .name = "pcm_spi1_cs2_128_grp",
+ .pins = pcm_spi1_cs2_128_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_cs2_128_pins0),
+ },
+ {
+ .name = "pcm_spi1_cs3_grp",
+ .pins = pcm_spi1_cs3_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_cs3_pins0),
+ },
+ {
+ .name = "pcm_spi1_cs4_grp",
+ .pins = pcm_spi1_cs4_pins0,
+ .num_pins = ARRAY_SIZE(pcm_spi1_cs4_pins0),
+ },
+ {
+ .name = "emmc",
+ .pins = emmc_pins0,
+ .num_pins = ARRAY_SIZE(emmc_pins0),
+ },
+ {
+ .name = "parallel_nand",
+ .pins = parallel_nand_pins0,
+ .num_pins = ARRAY_SIZE(parallel_nand_pins0),
+ },
+ {
+ .name = "lan0_led0_grp",
+ .pins = lan0_led0_pins0,
+ .num_pins = ARRAY_SIZE(lan0_led0_pins0),
+ },
+ {
+ .name = "lan0_led1_grp",
+ .pins = lan0_led1_pins0,
+ .num_pins = ARRAY_SIZE(lan0_led1_pins0),
+ },
+ {
+ .name = "lan1_led0_grp",
+ .pins = lan1_led0_pins0,
+ .num_pins = ARRAY_SIZE(lan1_led0_pins0),
+ },
+ {
+ .name = "lan1_led1_grp",
+ .pins = lan1_led1_pins0,
+ .num_pins = ARRAY_SIZE(lan1_led1_pins0),
+ },
+ {
+ .name = "lan2_led0_grp",
+ .pins = lan2_led0_pins0,
+ .num_pins = ARRAY_SIZE(lan2_led0_pins0),
+ },
+ {
+ .name = "lan2_led1_grp",
+ .pins = lan2_led1_pins0,
+ .num_pins = ARRAY_SIZE(lan2_led1_pins0),
+ },
+ {
+ .name = "lan3_led0_grp",
+ .pins = lan3_led0_pins0,
+ .num_pins = ARRAY_SIZE(lan3_led0_pins0),
+ },
+ {
+ .name = "lan3_led1_grp",
+ .pins = lan3_led1_pins0,
+ .num_pins = ARRAY_SIZE(lan3_led1_pins0),
+ },
+};
+
+static int an7581_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(an7581_pin_groups);
+}
+
+static const char *an7581_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ return an7581_pin_groups[group].name;
+}
+
+static int an7581_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ *pins = (unsigned int *)an7581_pin_groups[group].pins;
+ *num_pins = an7581_pin_groups[group].num_pins;
+ return 0;
+}
+
+static const struct pinctrl_ops an7581_pctrl_ops = {
+ .get_group_pins = an7581_get_group_pins,
+ .get_groups_count = an7581_get_groups_count,
+ .get_group_name = an7581_get_group_name,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+
+
+static const char * const pon0_groups[] = { "pon0_grp" };
+static const char * const tod_pon_groups[] = { "tod_pon_grp" };
+static const char * const tod_sw_groups[] = { "tod_sw_grp" };
+static const char * const sipo_groups[] = { "sipo_grp" };
+static const char * const sipo_rclk_groups[] = { "sipo_rclk_grp" };
+static const char * const i2c1_groups[] = { "i2c1_grp" };
+static const char * const sgmii_mdio_groups[] = { "mdio_grp" };
+static const char * const uart2_groups[] = { "uart2_grp" };
+static const char * const uart2_cts_rts_groups[] = { "uart2_cts_rts_grp" };
+static const char * const hsuart3_groups[] = { "hsuart3_grp" };
+static const char * const hsuart3_cts_rts_groups[] = { "hsuart3_cts_rts_grp" };
+static const char * const uart4_groups[] = { "uart4_grp" };
+static const char * const uart5_groups[] = { "uart5_grp" };
+//static const char * const i2c0_slave_groups[] = { "i2c0_slave_grp" };
+//static const char * const npu_uart_groups[] = { "npu_uart_grp" };
+static const char * const jtag_udi_groups[] = { "jtag_udi_grp" };
+static const char * const jtag_dfd_groups[] = { "jtag_dfd_grp" };
+static const char * const gpio_47_groups[] = { "gpio_47_grp" };
+static const char * const gpio_48_groups[] = { "gpio_48_grp" };
+static const char * const gpio_49_groups[] = { "gpio_49_grp" };
+static const char * const i2s_groups[] = { "i2s_grp" };
+static const char * const pcm1_groups[] = { "pcm1_grp" };
+static const char * const pcm2_groups[] = { "pcm2_grp" };
+static const char * const spi0_quad_groups[] = { "spi0_quad_grp" };
+static const char * const spi0_cs1_groups[] = { "spi0_cs1_grp" };
+static const char * const pcm_spi1_groups[] = { "pcm_spi1_grp" };
+static const char * const pcm_spi0_groups[] = { "pcm_spi0_grp" };
+static const char * const pcm_spi1_int_groups[] = { "pcm_spi1_int_grp" };
+static const char * const pcm_spi1_reset_groups[] = { "pcm_spi1_reset_grp" };
+static const char * const pcm_spi1_cs1_groups[] = { "pcm_spi1_cs1_grp" };
+static const char * const pcm_spi1_cs2_156_groups[] = { "pcm_spi1_cs2_156_grp" };
+static const char * const pcm_spi1_cs2_128_groups[] = { "pcm_spi1_cs2_128_grp" };
+static const char * const pcm_spi1_cs3_groups[] = { "pcm_spi1_cs3_grp" };
+static const char * const pcm_spi1_cs4_groups[] = { "pcm_spi1_cs4_grp" };
+static const char * const lan3_led1_groups[] = { "lan3_led1_grp" };
+static const char * const lan2_led1_groups[] = { "lan2_led1_grp" };
+static const char * const lan1_led1_groups[] = { "lan1_led1_grp" };
+static const char * const lan0_led1_groups[] = { "lan0_led1_grp" };
+static const char * const lan3_led0_groups[] = { "lan3_led0_grp" };
+static const char * const lan2_led0_groups[] = { "lan2_led0_grp" };
+static const char * const lan1_led0_groups[] = { "lan1_led0_grp" };
+static const char * const lan0_led0_groups[] = { "lan0_led0_grp" };
+
+
+static const struct an7581_pmx_func an7581_pmx_functions[] = {
+ {
+ .name = "pon0",
+ .groups = pon0_groups,
+ .num_groups = ARRAY_SIZE(pon0_groups),
+ .configs = { RG_GPIO_PON_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pon0_off",
+ .groups = pon0_groups,
+ .num_groups = ARRAY_SIZE(pon0_groups),
+ .configs = { RG_GPIO_PON_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "tod_pon",
+ .groups = tod_pon_groups,
+ .num_groups = ARRAY_SIZE(tod_pon_groups),
+ .configs = { RG_PON_TOD_1PPS_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "tod_sw",
+ .groups = tod_sw_groups,
+ .num_groups = ARRAY_SIZE(tod_sw_groups),
+ .configs = { RG_SW_TOD_1PPS_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "sipo",
+ .groups = sipo_groups,
+ .num_groups = ARRAY_SIZE(sipo_groups),
+ .configs = { RG_SIPO_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "sipo_rclk",
+ .groups = sipo_rclk_groups,
+ .num_groups = ARRAY_SIZE(sipo_rclk_groups),
+ .configs = { RG_SIPO_MODE, RG_SIPO_RCLK_MODE },
+ .num_configs = 2,
+ },
+ {
+ .name = "mdio",
+ .groups = sgmii_mdio_groups,
+ .num_groups = ARRAY_SIZE(sgmii_mdio_groups),
+ .configs = { RG_GPIO_SGMII_MDIO_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "uart2",
+ .groups = uart2_groups,
+ .num_groups = ARRAY_SIZE(uart2_groups),
+ .configs = { RG_GPIO_UART2_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "uart2_cts_rts",
+ .groups = uart2_groups,
+ .num_groups = ARRAY_SIZE(uart2_cts_rts_groups),
+ .configs = { RG_GPIO_UART2_CTS_RTS_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "hsuart3",
+ .groups = hsuart3_groups,
+ .num_groups = ARRAY_SIZE(hsuart3_groups),
+ .configs = { RG_GPIO_HSUART3_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "hsuart3_cts_rts",
+ .groups = hsuart3_cts_rts_groups,
+ .num_groups = ARRAY_SIZE(hsuart3_cts_rts_groups),
+ .configs = { RG_GPIO_HSUART3_CTS_RTS_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "uart4",
+ .groups = uart4_groups,
+ .num_groups = ARRAY_SIZE(uart4_groups),
+ .configs = { RG_GPIO_UART4_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "uart5",
+ .groups = uart5_groups,
+ .num_groups = ARRAY_SIZE(uart5_groups),
+ .configs = { RG_GPIO_UART5_MODE },
+ .num_configs = 1,
+ },
+// {
+// .name = "npu_uart",
+// .groups = npu_uart_groups,
+// .num_groups = ARRAY_SIZE(npu_uart_groups),
+// .configs = { RG_NPU_UART_EN },
+// .num_configs = 1,
+// },
+ {
+ .name = "i2c1",
+ .groups = i2c1_groups,
+ .num_groups = ARRAY_SIZE(i2c1_groups),
+ .configs = { RG_GPIO_2ND_I2C_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "jtag_udi",
+ .groups = jtag_udi_groups,
+ .num_groups = ARRAY_SIZE(jtag_udi_groups),
+ .configs = { RG_UDI_EJTAG_EN },
+ .num_configs = 1,
+ },
+ {
+ .name = "jtag_dfd",
+ .groups = jtag_dfd_groups,
+ .num_groups = ARRAY_SIZE(jtag_dfd_groups),
+ .configs = { RG_DFD_EJTAG_EN },
+ .num_configs = 1,
+ },
+ {
+ .name = "gpio_47",
+ .groups = gpio_47_groups,
+ .num_groups = ARRAY_SIZE(gpio_47_groups),
+ .configs = { RG_PCIE_RESET0_GPIO_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "gpio_48",
+ .groups = gpio_48_groups,
+ .num_groups = ARRAY_SIZE(gpio_48_groups),
+ .configs = { RG_PCIE_RESET1_GPIO_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "gpio_49",
+ .groups = gpio_49_groups,
+ .num_groups = ARRAY_SIZE(gpio_49_groups),
+ .configs = { RG_PCIE_RESET2_GPIO_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm1",
+ .groups = pcm1_groups,
+ .num_groups = ARRAY_SIZE(pcm1_groups),
+ .configs = { RG_GPIO_PCM1_MODE },
+ .num_configs = 3,
+ },
+ {
+ .name = "pcm2",
+ .groups = pcm2_groups,
+ .num_groups = ARRAY_SIZE(pcm2_groups),
+ .configs = { RG_GPIO_PCM2_MODE },
+ .num_configs = 3,
+ },
+ {
+ .name = "spi0_quad",
+ .groups = spi0_quad_groups,
+ .num_groups = ARRAY_SIZE(spi0_quad_groups),
+ .configs = { RG_GPIO_SPI_QUAD_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "spi0_cs1",
+ .groups = spi0_cs1_groups,
+ .num_groups = ARRAY_SIZE(spi0_cs1_groups),
+ .configs = { RG_GPIO_SPI_CS1_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1",
+ .groups = pcm_spi1_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_groups),
+ .configs = { RG_GPIO_PCM_SPI_MODE },
+ .num_configs = 2,
+ },
+ {
+ .name = "pcm_spi0",
+ .groups = pcm_spi0_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi0_groups),
+ .configs = { RG_GPIO_PCM_SPI_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_int",
+ .groups = pcm_spi1_int_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_int_groups),
+ .configs = { RG_GPIO_PCM_INT_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_reset",
+ .groups = pcm_spi1_reset_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_reset_groups),
+ .configs = { RG_GPIO_PCM_RESET_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_cs1",
+ .groups = pcm_spi1_cs1_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_cs1_groups),
+ .configs = { RG_GPIO_PCM_SPI_CS1_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_cs2_156",
+ .groups = pcm_spi1_cs2_156_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_cs2_156_groups),
+ .configs = { RG_GPIO_PCM_SPI_CS2_MODE_156PIN },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_cs2_128",
+ .groups = pcm_spi1_cs2_128_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_cs2_128_groups),
+ .configs = { RG_GPIO_PCM_SPI_CS2_MODE_128PIN },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_cs3",
+ .groups = pcm_spi1_cs3_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_cs3_groups),
+ .configs = { RG_GPIO_PCM_SPI_CS3_MODE },
+ .num_configs = 1,
+ },
+ {
+ .name = "pcm_spi1_cs4",
+ .groups = pcm_spi1_cs4_groups,
+ .num_groups = ARRAY_SIZE(pcm_spi1_cs4_groups),
+ .configs = { RG_GPIO_PCM_SPI_CS4_MODE },
+ .num_configs = 1,
+ },
+
+ // Functions to disable default set leds
+ {
+ .name = "lan0_led0_disable",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan1_led0_disable",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan2_led0_disable",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan3_led0_disable",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan0_led1_disable",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan1_led1_disable",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan2_led1_disable",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ {
+ .name = "lan3_led1_disable",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE },
+ .num_configs = 1,
+ .unset = 1,
+ },
+ // LAN0_LED0
+ {
+ .name = "lan0_led0_to_lan0_led0",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE, RG_LAN0_LED0_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led0_to_lan1_led0",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE, RG_LAN0_LED0_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led0_to_lan2_led0",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE, RG_LAN0_LED0_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led0_to_lan3_led0",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE, RG_LAN0_LED0_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led0_to_lan4_led0",
+ .groups = lan0_led0_groups,
+ .num_groups = ARRAY_SIZE(lan0_led0_groups),
+ .configs = { RG_GPIO_LAN0_LED0_MODE, RG_LAN0_LED0_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+ // LAN0_LED1
+ {
+ .name = "lan0_led1_to_lan0_led1",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE, RG_LAN0_LED1_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led1_to_lan1_led1",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE, RG_LAN0_LED1_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led1_to_lan2_led1",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE, RG_LAN0_LED1_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led1_to_lan3_led1",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE, RG_LAN0_LED1_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan0_led1_to_lan4_led1",
+ .groups = lan0_led1_groups,
+ .num_groups = ARRAY_SIZE(lan0_led1_groups),
+ .configs = { RG_GPIO_LAN0_LED1_MODE, RG_LAN0_LED1_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+
+ // LAN1_LED0
+ {
+ .name = "lan1_led0_to_lan0_led0",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE, RG_LAN1_LED0_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led0_to_lan1_led0",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE, RG_LAN1_LED0_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led0_to_lan2_led0",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE, RG_LAN1_LED0_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led0_to_lan3_led0",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE, RG_LAN1_LED0_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led0_to_lan4_led0",
+ .groups = lan1_led0_groups,
+ .num_groups = ARRAY_SIZE(lan1_led0_groups),
+ .configs = { RG_GPIO_LAN1_LED0_MODE, RG_LAN1_LED0_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+ // LAN1_LED1
+ {
+ .name = "lan1_led1_to_lan0_led1",
+ .groups = lan1_led1_groups,
+ .num_groups = ARRAY_SIZE(lan1_led1_groups),
+ .configs = { RG_GPIO_LAN1_LED1_MODE, RG_LAN1_LED1_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led1_to_lan1_led1",
+ .groups = lan1_led1_groups,
+ .num_groups = ARRAY_SIZE(lan1_led1_groups),
+ .configs = { RG_GPIO_LAN1_LED1_MODE, RG_LAN1_LED1_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led1_to_lan2_led1",
+ .groups = lan1_led1_groups,
+ .num_groups = ARRAY_SIZE(lan1_led1_groups),
+ .configs = { RG_GPIO_LAN1_LED1_MODE, RG_LAN1_LED1_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led1_to_lan3_led1",
+ .groups = lan1_led1_groups,
+ .num_groups = ARRAY_SIZE(lan1_led1_groups),
+ .configs = { RG_GPIO_LAN1_LED1_MODE, RG_LAN1_LED1_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan1_led1_to_lan4_led1",
+ .groups = lan1_led1_groups,
+ .num_groups = ARRAY_SIZE(lan1_led1_groups),
+ .configs = { RG_GPIO_LAN1_LED1_MODE, RG_LAN1_LED1_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+
+ // LAN2_LED0
+ {
+ .name = "lan2_led0_to_lan0_led0",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE, RG_LAN2_LED0_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led0_to_lan1_led0",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE, RG_LAN2_LED0_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led0_to_lan2_led0",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE, RG_LAN2_LED0_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led0_to_lan3_led0",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE, RG_LAN2_LED0_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led0_to_lan4_led0",
+ .groups = lan2_led0_groups,
+ .num_groups = ARRAY_SIZE(lan2_led0_groups),
+ .configs = { RG_GPIO_LAN2_LED0_MODE, RG_LAN2_LED0_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+ // LAN2_LED1
+ {
+ .name = "lan2_led1_to_lan0_led1",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE, RG_LAN2_LED1_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led1_to_lan1_led1",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE, RG_LAN2_LED1_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led1_to_lan2_led1",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE, RG_LAN2_LED1_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led1_to_lan3_led1",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE, RG_LAN2_LED1_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan2_led1_to_lan4_led1",
+ .groups = lan2_led1_groups,
+ .num_groups = ARRAY_SIZE(lan2_led1_groups),
+ .configs = { RG_GPIO_LAN2_LED1_MODE, RG_LAN2_LED1_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+
+ // LAN3_LED0
+ {
+ .name = "lan3_led0_to_lan0_led0",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE, RG_LAN3_LED0_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led0_to_lan1_led0",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE, RG_LAN3_LED0_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led0_to_lan2_led0",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE, RG_LAN3_LED0_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led0_to_lan3_led0",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE, RG_LAN3_LED0_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led0_to_lan4_led0",
+ .groups = lan3_led0_groups,
+ .num_groups = ARRAY_SIZE(lan3_led0_groups),
+ .configs = { RG_GPIO_LAN3_LED0_MODE, RG_LAN3_LED0_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+ // LAN3_LED1
+ {
+ .name = "lan3_led1_to_lan0_led1",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE, RG_LAN3_LED1_MAPPING_LAN0 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led1_to_lan1_led1",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE, RG_LAN3_LED1_MAPPING_LAN1 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led1_to_lan2_led1",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE, RG_LAN3_LED1_MAPPING_LAN2 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led1_to_lan3_led1",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE, RG_LAN3_LED1_MAPPING_LAN3 },
+ .num_configs = 2,
+ },
+ {
+ .name = "lan3_led1_to_lan4_led1",
+ .groups = lan3_led1_groups,
+ .num_groups = ARRAY_SIZE(lan3_led1_groups),
+ .configs = { RG_GPIO_LAN3_LED1_MODE, RG_LAN3_LED1_MAPPING_LAN4 },
+ .num_configs = 2,
+ },
+
+};
+
+
+
+static int an7581_get_settings_regs(unsigned int pin) {
+ int i;
+ for (i=0 ; i<ARRAY_SIZE(an7581_pin_settings) ; i++) {
+ if (pin == an7581_pin_settings[i].pin_idx) return i;
+ }
+ return -1;
+}
+
+
+static int an7581_reg_mask_get(struct an7581_pmx *pmx, unsigned int reg_identity) {
+ int i;
+ u32 regval;
+ void __iomem *reg;
+
+ for (i=0 ; i<ARRAY_SIZE(an7581_registers) ; i++) {
+ if (reg_identity == an7581_registers[i].reg_id) {
+ reg = pmx->mux_regs[an7581_registers[i].reg_idx];
+ regval = ioread32(reg);
+ if (regval & an7581_registers[i].reg_mask)
+ return 1;
+ else
+ return 0;
+ }
+ }
+ return -1;
+}
+
+static void an7581_reg_mask_set(struct an7581_pmx *pmx, unsigned int reg_identity, int toggle) {
+ int i;
+ u32 regval;
+ void __iomem *reg;
+
+ for (i=0 ; i<ARRAY_SIZE(an7581_registers) ; i++) {
+ if (reg_identity == an7581_registers[i].reg_id) {
+ reg = pmx->mux_regs[an7581_registers[i].reg_idx];
+ regval = ioread32(reg);
+ dev_dbg(pmx->dev, "register[%d] 0x%08x and regvalue 0x%08x mask 0x%08x toggle %d\n", i, reg, regval, an7581_registers[i].reg_mask, toggle);
+
+ if (toggle == 1) {
+ regval |= an7581_registers[i].reg_mask;
+ } else {
+ regval &= ~(an7581_registers[i].reg_mask);
+ }
+ iowrite32(regval, reg);
+ }
+ }
+ return;
+}
+
+static int an7581_pmx_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(an7581_pmx_functions);
+}
+
+static const char *an7581_pmx_get_fname(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ return an7581_pmx_functions[function].name;
+}
+
+static int an7581_pmx_get_fgroups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ *groups = an7581_pmx_functions[function].groups;
+ *num_groups = an7581_pmx_functions[function].num_groups;
+ return 0;
+}
+
+static void an7581_pmx_select_func(struct pinctrl_dev *pctldev,
+ unsigned int function, unsigned int group,
+ bool enable)
+{
+ int i, reg, unset;
+ struct an7581_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ for (i = 0; i < an7581_pmx_functions[function].num_configs; i++) {
+ dev_dbg(pmx->dev, "function %d and group %d enabled\n", function, group);
+ reg = an7581_pmx_functions[function].configs[i];
+ if (an7581_pmx_functions[function].unset)
+ an7581_reg_mask_set(pmx, reg, 0);
+ else
+ an7581_reg_mask_set(pmx, reg, 1);
+ }
+}
+
+
+static int an7581_pmx_set(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct an7581_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+
+ dev_info(pmx->dev, "enabling %s function for pin group %s\n",
+ an7581_pmx_get_fname(pctldev, function),
+ an7581_get_group_name(pctldev, group));
+
+ an7581_pmx_select_func(pctldev, function, group, true);
+
+ return 0;
+}
+
+
+static int an7581_pmx_request_gpio(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct an7581_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+// u32 val;
+ int pin_idx, gpio;
+
+ /* Get settings registers for pin */
+ pin_idx = an7581_get_settings_regs(pin);
+
+ if (pin_idx < 0) {
+ dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
+ pmx->pins[pin].name);
+ return -ENOTSUPP;
+ }
+
+ gpio = an7581_pin_settings[pin_idx].gpio;
+ an7581_reg_mask_set(pmx, gpio, 1);
+
+ return 0;
+}
+
+static const struct pinmux_ops an7581_pmx_ops = {
+ .get_functions_count = an7581_pmx_get_functions_count,
+ .get_function_name = an7581_pmx_get_fname,
+ .get_function_groups = an7581_pmx_get_fgroups,
+ .set_mux = an7581_pmx_set,
+ .gpio_request_enable = an7581_pmx_request_gpio,
+};
+
+
+static int an7581_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct an7581_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ unsigned int regval;
+ int pin_idx, reg_mask_idx;
+ int pull_down, pull_up, drive_e2, drive_e4;
+
+ /* Check for valid pin */
+ if (pin >= pmx->num_pins) {
+ dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
+ pmx->pins[pin].name);
+ return -ENOTSUPP;
+ }
+
+ /* Get settings registers for pin */
+ pin_idx = an7581_get_settings_regs(pin);
+
+ if (pin_idx < 0) {
+ dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
+ pmx->pins[pin].name);
+ return -ENOTSUPP;
+ }
+
+ /* Get pin settings registers and mask index */
+ pull_down = an7581_pin_settings[reg_mask_idx].pull_down;
+ pull_up = an7581_pin_settings[reg_mask_idx].pull_up;
+ drive_e2 = an7581_pin_settings[reg_mask_idx].drive_e2;
+ drive_e4 = an7581_pin_settings[reg_mask_idx].drive_e4;
+
+ dev_dbg(pmx->dev, "getting configuration for pin %s\n",
+ pmx->pins[pin].name);
+
+ /* If valid, get configuration for parameter */
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (!((an7581_reg_mask_get(pmx, pull_up) == 0) &&
+ (an7581_reg_mask_get(pmx, pull_down) == 0)))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (!((an7581_reg_mask_get(pmx, pull_up) == 1) &&
+ (an7581_reg_mask_get(pmx, pull_down) == 0)))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (!((an7581_reg_mask_get(pmx, pull_up) == 0) &&
+ (an7581_reg_mask_get(pmx, pull_down) == 1)))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ int e2 = an7581_reg_mask_get(pmx, drive_e2);
+ int e4 = an7581_reg_mask_get(pmx, drive_e4);
+ regval = (e4<<1) | e2;
+ *config = pinconf_to_config_packed(param, regval);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ return 0;
+}
+
+/*
+ * Valid combinations of param and arg:
+ *
+ * param arg
+ * PIN_CONFIG_BIAS_DISABLE: x (disable bias)
+ * PIN_CONFIG_BIAS_PULL_UP: 1 (pull up bias + enable)
+ * PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
+ * PIN_CONFIG_DRIVE_STRENGTH: x (2mA, 4mA, 6mA, 8mA)
+ *
+ * All other args are invalid. All other params are not supported.
+ */
+static int an7581_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct an7581_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param;
+ unsigned int arg;
+ int i, pin_idx;
+ int pull_down, pull_up, drive_e2, drive_e4;
+
+ /* Check for valid pin */
+ if (pin >= pmx->num_pins) {
+ dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
+ pmx->pins[pin].name);
+ return -ENOTSUPP;
+ }
+
+ /* Get settings registers for pin */
+ pin_idx = an7581_get_settings_regs(pin);
+
+ if (pin_idx < 0) {
+ dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
+ pmx->pins[pin].name);
+ return -ENOTSUPP;
+ }
+
+ /* Get pin settings registers and mask index */
+ pull_down = an7581_pin_settings[pin_idx].pull_down;
+ pull_up = an7581_pin_settings[pin_idx].pull_up;
+ drive_e2 = an7581_pin_settings[pin_idx].drive_e2;
+ drive_e4 = an7581_pin_settings[pin_idx].drive_e4;
+
+ dev_info(pmx->dev, "setting configuration for pin %s\n",
+ pmx->pins[pin].name);
+
+ /* For each config */
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ an7581_reg_mask_set(pmx, pull_up, 0);
+ an7581_reg_mask_set(pmx, pull_down, 0);
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (arg != 1) {
+ dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
+ __func__, arg);
+ return -EINVAL;
+ }
+ an7581_reg_mask_set(pmx, pull_up, 1);
+ an7581_reg_mask_set(pmx, pull_down, 0);
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if (arg != 1) {
+ dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
+ __func__, arg);
+ return -EINVAL;
+ }
+ an7581_reg_mask_set(pmx, pull_down, 1);
+ an7581_reg_mask_set(pmx, pull_up, 0);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ switch (arg) {
+ case AN7581_DRIVE_2mA:
+ an7581_reg_mask_set(pmx, drive_e2, 0);
+ an7581_reg_mask_set(pmx, drive_e4, 0);
+ break;
+ case AN7581_DRIVE_4mA:
+ an7581_reg_mask_set(pmx, drive_e2, 1);
+ an7581_reg_mask_set(pmx, drive_e4, 0);
+ break;
+ case AN7581_DRIVE_6mA:
+ an7581_reg_mask_set(pmx, drive_e2, 0);
+ an7581_reg_mask_set(pmx, drive_e4, 1);
+ break;
+ case AN7581_DRIVE_8mA:
+ an7581_reg_mask_set(pmx, drive_e2, 1);
+ an7581_reg_mask_set(pmx, drive_e4, 1);
+ break;
+ default:
+ dev_dbg(pmx->dev, "%s argument %u not supported\n", __func__, arg);
+ return -ENOTSUPP;
+ }
+ break;
+
+ default:
+ dev_dbg(pmx->dev, "parameter not supported\n");
+ return -ENOTSUPP;
+ }
+ }
+ return 0;
+}
+
+static int an7581_pconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *configs,
+ unsigned int num_configs)
+{
+ unsigned int num_pins, current_pin;
+ int ret;
+
+ dev_dbg(pctldev->dev, "setting group %s configuration\n",
+ an7581_get_group_name(pctldev, group));
+
+ num_pins = an7581_pin_groups[group].num_pins;
+
+ for (current_pin = 0; current_pin < num_pins; current_pin++) {
+ ret = an7581_pconf_set(pctldev,
+ an7581_pin_groups[group].pins[current_pin],
+ configs, num_configs);
+
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+};
+
+
+static const struct pinconf_ops an7581_pconf_ops = {
+ .is_generic = true,
+ .pin_config_get = an7581_pconf_get,
+ .pin_config_set = an7581_pconf_set,
+ .pin_config_group_set = an7581_pconf_group_set,
+};
+
+static struct pinctrl_desc an7581_desc = {
+ .name = "an7581-pinctrl",
+ .owner = THIS_MODULE,
+ .pins = an7581_pins,
+ .npins = ARRAY_SIZE(an7581_pins),
+ .pctlops = &an7581_pctrl_ops,
+ .pmxops = &an7581_pmx_ops,
+ .confops = &an7581_pconf_ops,
+};
+
+static int an7581_pmx_probe(struct platform_device *pdev)
+{
+ struct an7581_pmx *pmx;
+ void __iomem *tmp_reg_base;
+ int i, m=0;
+ u32 regval;
+ void __iomem *reg;
+ struct resource *res;
+
+ pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
+ if (!pmx)
+ return -ENOMEM;
+
+ pmx->dev = &pdev->dev;
+
+ /* Load registers from dts */
+ /* IOMUX Control Registers */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ for ( i=0 ; i<8 ; i++, m++) {
+ pmx->mux_regs[m] = ioremap(res->start+ i*sizeof(u32), resource_size(res));
+ dev_dbg(&pdev->dev, "mapping[%d] 0x%08x to regval: 0x%px\n", m, res->start+ i*sizeof(u32), pmx->mux_regs[i]);
+ }
+ /* IO TX Driving Control Registers */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ for ( i=0 ; i<6 ; i++, m++) {
+ pmx->mux_regs[m] = ioremap(res->start+ i*sizeof(u32), resource_size(res));
+ dev_dbg(&pdev->dev, "mapping[%d] 0x%08x to regval: 0x%px\n", m, res->start+ i*sizeof(u32), pmx->mux_regs[i]);
+ }
+ /* IO Pull up/down Control Registers */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ for ( i=0 ; i<6 ; i++, m++) {
+ pmx->mux_regs[m] = ioremap(res->start+ i*sizeof(u32), resource_size(res));
+ dev_dbg(&pdev->dev, "mapping[%d] 0x%08x to regval: 0x%px\n", m, res->start+ i*sizeof(u32), pmx->mux_regs[i]);
+ }
+ /* LED Mux Mapping Register */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
+ for ( i=0 ; i<2 ; i++, m++) {
+ pmx->mux_regs[m] = ioremap(res->start+ i*sizeof(u32), resource_size(res));
+ dev_dbg(&pdev->dev, "mapping[%d] 0x%08x to regval: 0x%px\n", m, res->start+ i*sizeof(u32), pmx->mux_regs[i]);
+ }
+
+ for ( i=0 ; i<MUX_REG_MAX ; i++) {
+ reg = pmx->mux_regs[i];
+ regval = ioread32(reg);
+ dev_dbg(&pdev->dev, "pmux registers: 0x%px regval: 0x%08x\n", pmx->mux_regs[i], regval);
+ }
+
+ pmx->pins = an7581_pins;
+ pmx->num_pins = ARRAY_SIZE(an7581_pins);
+ pmx->functions = an7581_pmx_functions;
+ pmx->num_functions = ARRAY_SIZE(an7581_pmx_functions);
+ pmx->pin_groups = an7581_pin_groups;
+ pmx->num_pin_groups = ARRAY_SIZE(an7581_pin_groups);
+ pmx->pctl = pinctrl_register(&an7581_desc, &pdev->dev, pmx);
+
+ if (IS_ERR(pmx->pctl)) {
+ dev_err(&pdev->dev, "could not register pinctrl driver\n");
+ return PTR_ERR(pmx->pctl);
+ }
+
+ platform_set_drvdata(pdev, pmx);
+
+ dev_info(&pdev->dev, "initialised Airoha AN7581 pinctrl driver\n");
+
+ return 0;
+}
+
+static int an7581_pmx_remove(struct platform_device *pdev)
+{
+ struct an7581_pmx *pmx = platform_get_drvdata(pdev);
+
+ pinctrl_unregister(pmx->pctl);
+
+ return 0;
+}
+
+static const struct of_device_id an7581_pinctrl_match[] = {
+ { .compatible = "airoha,an7581-pinctrl", },
+ { }
+};
+
+static struct platform_driver an7581_pmx_driver = {
+ .driver = {
+ .name = "an7581-pctl_probe",
+ .of_match_table = an7581_pinctrl_match,
+ },
+ .probe = an7581_pmx_probe,
+ .remove = an7581_pmx_remove,
+};
+
+module_platform_driver(an7581_pmx_driver);
+
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_DESCRIPTION("AN7581 pinctrl driver");
+MODULE_LICENSE("GPL v2");
--
2.34.1
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