1373 lines
43 KiB
C
Executable File
1373 lines
43 KiB
C
Executable File
/***************************************************************
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Copyright Statement:
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This software/firmware and related documentation (EcoNet Software)
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are protected under relevant copyright laws. The information contained herein
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is confidential and proprietary to EcoNet (HK) Limited (EcoNet) and/or
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its licensors. Without the prior written permission of EcoNet and/or its licensors,
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any reproduction, modification, use or disclosure of EcoNet Software, and
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information contained herein, in whole or in part, shall be strictly prohibited.
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EcoNet (HK) Limited EcoNet. ALL RIGHTS RESERVED.
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BY OPENING OR USING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY
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ACKNOWLEDGES AND AGREES THAT THE SOFTWARE/FIRMWARE AND ITS
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DOCUMENTATIONS (ECONET SOFTWARE) RECEIVED FROM ECONET
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AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON AN AS IS
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BASIS ONLY. ECONET EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
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WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
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WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
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OR NON-INFRINGEMENT. NOR DOES ECONET PROVIDE ANY WARRANTY
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WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTIES WHICH
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MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE ECONET SOFTWARE.
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RECEIVER AGREES TO LOOK ONLY TO SUCH THIRD PARTIES FOR ANY AND ALL
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WARRANTY CLAIMS RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
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THAT IT IS RECEIVERS SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD
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PARTY ALL PROPER LICENSES CONTAINED IN ECONET SOFTWARE.
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ECONET SHALL NOT BE RESPONSIBLE FOR ANY ECONET SOFTWARE RELEASES
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MADE TO RECEIVERS SPECIFICATION OR CONFORMING TO A PARTICULAR
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STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND
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ECONET'S ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE ECONET
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SOFTWARE RELEASED HEREUNDER SHALL BE, AT ECONET'S SOLE OPTION, TO
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REVISE OR REPLACE THE ECONET SOFTWARE AT ISSUE OR REFUND ANY SOFTWARE
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LICENSE FEES OR SERVICE CHARGES PAID BY RECEIVER TO ECONET FOR SUCH
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ECONET SOFTWARE.
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***************************************************************/
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///@file libapi_lib_switchmgr.h
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///@brief Switch Module API
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#ifndef _API_LIB_SWITCHMGR_H
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#define _API_LIB_SWITCHMGR_H
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/************************************************************************
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* C O N S T A N T S
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*************************************************************************
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*/
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///@brief Return value of switch API
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typedef enum
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{
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ECNT_SWITCHMGR_SUCCESS = 0, /**< api execution success */
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ECNT_SWITCHMGR_FAIL, /**< api execution fail */
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}ECNT_SWITCHMGR_RET;
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///@brief Device chip type
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typedef enum
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{
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ECNT_SWITCH_CHIP_MT7520S = 0, /**< MT7520S */
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ECNT_SWITCH_CHIP_MT7520F = 1, /**< MT7520F */
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ECNT_SWITCH_CHIP_MT7520G = 2, /**< MT7520G */
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ECNT_SWITCH_CHIP_MT7525F = 3, /**< MT7525S */
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ECNT_SWITCH_CHIP_MT7525G = 4, /**< MT7525G */
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ECNT_SWITCH_CHIP_EN7521F = 5, /**< EN7521F */
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ECNT_SWITCH_CHIP_EN7526F = 6, /**< EN7526F */
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ECNT_SWITCH_CHIP_EN751627 = 7, /**< EN751627 */
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ECNT_SWITCH_CHIP_EN7528 = 8, /**< EN7528 */
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ECNT_SWITCH_CHIP_EN7580 = 10, /**< EN7580 */
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}ECNT_SWITCHMGR_CHIP_TYPE;
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///@brief Port stp status
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typedef enum
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{
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ECNT_SWITCHMGR_STP_DISABLED = 0, /**< all packets discarded */
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ECNT_SWITCHMGR_STP_BLOCKING = 1, /**< only recv BPDU, discard all other packets */
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ECNT_SWITCHMGR_STP_LEARNING = 2, /**< recv BPDU, discard all other packets but do mac learning */
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ECNT_SWITCHMGR_STP_FORWARDING = 3, /**< forward all packets, */
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ECNT_SWITCHMGR_STP_PORT_LINKDOWN = 5, /**< link is down, this value is only for get action */
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ECNT_SWITCHMGR_STP_STATUS_MAX
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}ECNT_SWITCHMGR_STP_STATUS;
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///@brief Port speed mode configuration
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typedef enum
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{
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ECNT_SWITCHMGR_SPEED_MODE_AUTONEG = 1, /**< auto negotiation */
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ECNT_SWITCHMGR_SPEED_MODE_100M_FULL = 2, /**< 100M Full Duplex */
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ECNT_SWITCHMGR_SPEED_MODE_100M_HALF = 3, /**< 100M Half Duplex */
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ECNT_SWITCHMGR_SPEED_MODE_10M_FULL = 4, /**< 10M Full Duplex*/
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ECNT_SWITCHMGR_SPEED_MODE_10M_HALF = 5, /**< 10M Half Duplex */
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ECNT_SWITCHMGR_SPEED_MODE_MAX,
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}ECNT_SWITCHMGR_SPEED_MODE;
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///@brief Port link speed state
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typedef enum
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{
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ECNT_SWITCHMGR_LINK_SPEED_1000M_FULL = 1, /**< 1000M Full Duplex */
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ECNT_SWITCHMGR_LINK_SPEED_100M_FULL = 2, /**< 100M Full Duplex */
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ECNT_SWITCHMGR_LINK_SPEED_100M_HALF = 3, /**< 100M Half Duplex */
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ECNT_SWITCHMGR_LINK_SPEED_10M_FULL = 4, /**< 10M Full Duplex*/
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ECNT_SWITCHMGR_LINK_SPEED_10M_HALF = 5, /**< 10M Half Duplex */
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ECNT_SWITCHMGR_LINK_SPEED_1000M_HALF = 6, /**< 1000M Half Duplex */
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}ECNT_SWITCHMGR_LINK_SPEED;
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///@brief Port link state
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typedef enum
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{
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ECNT_SWITCHMGR_LINK_DOWN = 0, /**< link up */
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ECNT_SWITCHMGR_LINK_UP = 1, /**< link down */
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}ECNT_SWITCHMGR_LINK_STATE;
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/************************************************************************
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* M A C R O S
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*************************************************************************
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*/
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///@brief switch port number
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#define ECNT_SWITCHMGR_PORT_NUM 7
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///@brief switch port mac limit value for no limit
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#define ECNT_SWITCHMGR_PORT_MAC_LIMIT_VALUE_NO_LIMIT 0xFFF
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///@brief maximum mac acl rule number
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#define ECNT_SWITCHMGR_TRTCM_MATCH_MAC_RULE_NUM 10
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/************************************************************************
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* D A T A T Y P E S
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*************************************************************************
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*/
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#ifndef _u8_defined
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#define _u8_defined
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typedef unsigned char u8;
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#endif
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#ifndef _u16_defined
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#define _u16_defined
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typedef unsigned short u16;
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#endif
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#ifndef _u32_defined
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#define _u32_defined
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typedef unsigned int u32;
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#endif
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///@brief Port statistics
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typedef struct
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{
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u32 TxPktsCnt; /**< tx packet count */
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u32 TxUniPktsCnt; /**< tx unicast packet count */
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u32 TxBroadPktsCnt; /**< tx broadcast packet count */
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u32 TxMultiPktsCnt; /**< tx multicast packet count */
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u32 TxNonUniPktsCnt; /**< tx not unicast packet count */
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u32 TxBytesCnt_Lo; /**< tx bytes count (low 32bit) */
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u32 TxBytesCnt_Hi; /**< tx bytes count (high 32bit) */
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u32 TxUnderSizePktsCnt; /**< tx undersize packet count */
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u32 Tx64BytePktsCnt; /**< tx 64 byte packet count */
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u32 Tx65_127BytePktsCnt; /**< tx 65~127 byte packet count */
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u32 Tx128_255BytePktsCnt; /**< tx 128~255 byte packet count */
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u32 Tx256_511BytePktsCnt; /**< tx 256~511 byte packet count */
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u32 Tx512_1023BytePktsCnt; /**< tx 512~1023 byte packet count */
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u32 Tx1024_MAXBytePktsCnt; /**< tx 1024~MAX byte packet count */
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u32 Tx1024_1518BytePktsCnt; /**< tx 1024~1518 byte packet count */
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u32 Tx1519_MAXBytePktsCnt; /**< tx 1518~MAX byte packet count */
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u32 TxOverSizePktsCnt; /**< tx oversize packet count */
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u32 TxDropFramesCnt; /**< tx drop frame count */
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u32 TxPauseFramesCnt; /**< tx pause frame count */
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u32 TxCRCFramesCnt; /**< tx crc frame count */
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u32 TxSingleCollsionEvent; /**< tx single collision event count */
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u32 TxMultiCollsionEvent; /**< tx multi collision event count */
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u32 TxLateCollisionEvent; /**< tx late collision event count */
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u32 TxExcessCollisionEvent; /**< tx excessive collision event count */
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u32 TxDeferredEvent; /**< tx deferred event count */
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u32 TxOverFlowFrameCnt; /**< tx over flow frame count */
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u32 TxInternalMacErrorCnt; /**< tx internal mac error count */
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u32 TXCarrierSenseErrorCnt; /**< tx carrier sense error count */
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u32 RxPktsCnt; /**< rx packet count */
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u32 RxUniPktsCnt; /**< rx unicast packet count */
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u32 RxBroadPktsCnt; /**< rx broadcast packet count */
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u32 RxMultiPktsCnt; /**< rx multicast packet count */
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u32 RxNonUniPktsCnt; /**< rx not unicast packet count */
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u32 RxBytesCnt_Lo; /**< rx bytes count (low 32bit) */
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u32 RxBytesCnt_Hi; /**< rx bytes count (high 32bit) */
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u32 RxUnderSizePktsCnt; /**< rx undersize packet count */
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u32 Rx64BytePktsCnt; /**< rx 64 byte packet count */
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u32 Rx65_127BytePktsCnt; /**< rx 65~127 byte packet count */
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u32 Rx128_255BytePktsCnt; /**< rx 128~255 byte packet count */
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u32 Rx256_511BytePktsCnt; /**< rx 256~511 byte packet count */
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u32 Rx512_1023BytePktsCnt; /**< rx 512~1023 byte packet count */
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u32 Rx1024_MAXBytePktsCnt; /**< rx 1024~MAX byte packet count */
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u32 Rx1024_1518BytePktsCnt; /**< rx 1024~1518 byte packet count */
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u32 Rx1519_MAXBytePktsCnt; /**< rx 1519~MAX byte packet count */
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u32 RxOverSizePktsCnt; /**< rx oversize frame count */
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u32 RxDropFramesCnt; /**< rx drop frame count */
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u32 RxPauseFramesCnt; /**< rx pause frame count */
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u32 RxCRCFramesCnt; /**< rx crc frame count*/
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u32 RxOverFlowFrameCnt; /**< rx over flow frame count*/
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u32 RxFragmentErrorCnt; /**< rx fragment error count*/
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u32 RxJabberErrorCnt; /**< rx jabber error count*/
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u32 RxAlignmentErrorCnt; /**< rx allignment error count*/
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}ECNT_SWITCHMGR_PORT_STATISTICS;
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///@brief Mirror source port configuration
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typedef struct
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{
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u8 port; /**< lan port number as source mirror port */
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u8 tx_enable; /**< mirror tx to destination port */
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u8 rx_enable; /**< mirror rx to destination port */
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}ECNT_SWITCHMGR_LAN2LAN_SRC_PORT;
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///@brief Retrieve all switch configuration
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typedef struct
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{
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u8 enable; /**< global mirror enable/disable */
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ECNT_SWITCHMGR_LAN2LAN_SRC_PORT srcport[7]; /**< mirror source port */
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u8 srcportnum; /**< number of mirror source port enabled */
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u8 dstport; /**< global mirror destination port */
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}ECNT_SWITCHMGR_LAN2LAN_INFO;
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///@brief Mirror session configuration
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typedef struct
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{
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u8 srcport; /**< mirror source port */
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u8 tx_enable; /**< mirror tx to destination port */
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u8 rx_enable; /**< mirror rx to destination port */
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u8 dstport; /**< global mirror destination port */
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}ECNT_SWITCHMGR_LAN2LAN;
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///@brief Switch mac table entry
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typedef struct
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{
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u8 port; /**< switch port id*/
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u8 timer; /**< aging time */
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u8 mac[6]; /**< mac address */
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u16 vid; /**< vlan id */
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}ECNT_SWITCHMGR_MAC_ENTRY;
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///@brief Switch port qos mode configuration
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typedef struct
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{
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u8 qosmode; /**< qos mode */
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u8 wrr_queue_cnt; /**< wrr queue count */
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u8 wi[8]; /**< wrr queue weight */
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u8 eight_queue;
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}ECNT_SWITCHMGR_QOS_CFG;
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///@brief Switch mac table
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typedef struct
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{
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u32 count; /**< mac table entry count */
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ECNT_SWITCHMGR_MAC_ENTRY macinfo[2048]; /**< mac table entry */
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}ECNT_SWITCHMGR_BRIDGE_TABLE;
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///@brief Switch port queue buffer threshold
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typedef struct
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{
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u8 Enable; /**< enable */
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u32 time; /**< time in us, only for get action */
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u16 MaxQueueThreshold; /**< queue max threshold*/
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u16 MinQueueThreshold; /**< queue min threshold*/
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}ECNT_SWITCHMGR_QUEUE_BACK_PRESSURE;
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///@brief Switch mac table entry
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typedef struct
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{
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u8 mac[6]; /**< mac address */
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}ECNT_SWITCHMGR_PORT_MAC_ENTRY;
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///@brief Switch mac table
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typedef struct
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{
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u8 vaild_entry_num; /**< mac table entry number */
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ECNT_SWITCHMGR_PORT_MAC_ENTRY portmac[16]; /**< mac table entry */
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}ECNT_SWITCHMGR_PORT_ALL_MAC;
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///@brief TRTCM entry
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typedef struct
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{
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u8 trtcmId; /**< entry id */
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u16 CIR; /**< committed information rate */
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u16 PIR; /**< peak information rate */
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u16 CBS; /**< committed burst size */
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u16 PBS; /**< peak burst size */
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}ECNT_SWITCHMGR_TRTCM;
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///@brief TRTCM configuration
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typedef struct
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{
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u8 enable; /**< enable/disable */
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ECNT_SWITCHMGR_TRTCM trtcm_acl_table[32]; /**< TRTCM entry */
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}ECNT_SWITCHMGR_TRTCM_ACL;
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///@brief Switch mac entry
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typedef struct
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{
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u32 mac[6]; /**< destination mac address*/
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u32 destportmap; /**< destination port bitmap*/
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u32 leaky_en; /**< leaky enable */
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u32 eg_tag; /**< egress tag */
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u32 usr_pri; /**< user priority */
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u32 sa_mir_en; /**< source address mirror enable */
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u32 sa_port_fw; /**< source address forward port */
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}ECNT_SWITCHMGR_ARL_MAC_ENTRY;
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///@brief Switch vlan configuration
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typedef struct
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{
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u8 index; /**< index */
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u8 active; /**< active */
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u8 portMap; /**< port bitmap */
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u8 tagPortMap; /**< tag port bitmap */
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u16 vid; /**< vlan id */
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u8 ivl_en; /**< ivl enable */
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u8 fid; /**< fid */
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u16 stag; /**< stag */
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}ECNT_SWITCHMGR_VLAN_ENTRY;
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///@brief Mirror source port configuration
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typedef struct
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{
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u8 port_tx_mir; /**< mirror tx packet */
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u8 port_rx_mir; /**< mirror rx packet */
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u8 vlan_mis; /**< mirror vlan miss packet */
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u8 acl_mir; /**< mirror packet matching acl */
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u8 igmp_mir; /**< mirror igmp packet */
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}ECNT_SWITCHMGR_PORT_MIRROR;
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///@brief Switch qos drop policy
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typedef struct
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{
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u16 greenPacketDropQueueMaxThr; /**< queue max threshold of green packet drop */
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u16 greenPacketDropQueueMinThr; /**< queue min threshold of green packet drop */
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u16 yellowPacketDropQueueMaxThr; /**< queue max threshold of yellow packet drop */
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u16 yellowPacketDropQueueMinThr; /**< queue min threshold of yellow packet drop */
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u8 greenPacketDropMax_p; /**< green packet drop max page */
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u8 yellowPacketDropMaxn_p; /**< yellow packet drop max page */
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u8 QueueDropW_q; /**< queue drop page */
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u8 DropPrecdenceColourMarking; /**< drop precdence color marking */
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}ECNT_SWITCHMGR_DROP_POLICY;
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///@brief switch traffic descriptor configuration
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typedef struct
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{
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u32 CIR; /**< cir */
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u32 PIR; /**< pir */
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u32 CBS; /**< cbs */
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u32 PBS; /**< pbs */
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u8 colourMode; /**< color mode */
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u8 ingressColourMarking; /**< ingress color marking */
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u8 engressColourMarking; /**< egress color marking */
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u8 meterType; /**< meter type */
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u8 direction; /**< direction */
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}ECNT_SWITCHMGR_TRAFFIC_DESCRIPTOR;
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///@brief Switch timestamp
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typedef struct
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{
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u32 seconds; /**< second */
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u32 nanoseconds; /**< nano second*/
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}ECNT_SWITCHMGR_TIMESTAMP;
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///@brief Switch timestamp info
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typedef struct
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{
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ECNT_SWITCHMGR_TIMESTAMP tstamp; /**< switch time stamp */
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u8 msg_type; /**< message type */
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u8 seq_id; /**< sequence id */
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}ECNT_SWITCHMGR_TIMESTAMP_FIFO;
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///@brief Switch port queue weight
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typedef struct
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{
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u8 port; /**< lan port id */
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u8 weight[8]; /**< weight of queue0~7 */
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}ECNT_SWITCHMGR_PORT_WEIGHT;
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///@brief Entry of rate control by acl mac
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typedef struct
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{
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int dev_mac[6]; /**< match mac address */
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unsigned char ds_used; /**< not used */
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unsigned char mac_entry_index; /**< not used */
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int ds_queue_speed; /**< down stream speed */
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int us_queue_speed; /**< up stream speed*/
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}ECNT_SWITCHMGR_ACL_MAC_SPEED_ENTRY;
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///@brief Rate control by acl mac
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typedef struct
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{
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u8 enable; /**< enable/disable */
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ECNT_SWITCHMGR_ACL_MAC_SPEED_ENTRY trtcm_acl_mac_table[ECNT_SWITCHMGR_TRTCM_MATCH_MAC_RULE_NUM]; /**< mac acl entries */
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}ECNT_SWITCHMGR_DEV_SPEED;
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/************************************************************************
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* F U N C T I O N D E C L A R A T I O N S
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*************************************************************************
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*/
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ECNT_SWITCHMGR_RET switchmgr_lib_get_port_rx_byte(int port, unsigned int* RxByte_H, unsigned int* RxByte_L);
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ECNT_SWITCHMGR_RET switchmgr_lib_get_port_tx_byte(int port, unsigned int* TxByte_H, unsigned int* TxByte_L);
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/**
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@brief Set switch port mapping between lan(ether wan) ports and switch hw ports
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@param[in] wan_port switch hw port id for ether wan, range [-1, 6]
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@param[in] lan_portmap switch hw port id array for lan ports, range [-1, 6]
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@return ::ECNT_SWITCHMGR_RET
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@note when a wan_port or lan port is invalid, set the corresponding switch hw port id to -1.
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@par Supported Chip:
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@code
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EN7512, EN7521, EN7580
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@endcode
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@par Example:
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@code
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int ret = 0;
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int wan_port = -1;
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int lan_portmap[6] = {1, 2, 3, 4, -1, -1};
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ret = switchmgr_lib_set_portmap(wan_port, lan_portmap);
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@endcode
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*/
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ECNT_SWITCHMGR_RET switchmgr_lib_set_portmap(int wan_port, int lan_portmap[6]);
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ECNT_SWITCHMGR_RET switchmgr_lib_get_portmap(char *lan_portmap);
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/**
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@brief Set switch vlan function
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@param[in] enable enable/disable switch vlan function
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@return ::ECNT_SWITCHMGR_RET
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@par Supported Chip:
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@code
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EN7512, EN7521, EN7580
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@endcode
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*/
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ECNT_SWITCHMGR_RET switchmgr_lib_set_vlan_active(u8 enable);
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/**
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@brief Set switch global flow control
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@param[in] enable enable/disable switch global flow control
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@return ::ECNT_SWITCHMGR_RET
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@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_flow_control(u8 enable);
|
|
|
|
/**
|
|
@brief Get switch global flow control
|
|
@param[out] p_enable global flow control enable/disable
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_flow_control(u8 *p_enable);
|
|
|
|
/**
|
|
@brief Set switch port maximum frame size
|
|
@param[in] size maximum frame size
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_max_framesize(u16 size);
|
|
|
|
/**
|
|
@brief Get switch port maximum frame size
|
|
@param[out] p_size maximum frame size
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_max_framesize(u16 *p_size);
|
|
|
|
/**
|
|
@brief Set switch port isolate
|
|
@param[in] enable enable/disable switch port isolate
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_isolate(u8 enable);
|
|
|
|
/**
|
|
@brief Set switch port matrix
|
|
@param[in] type port group type:\n
|
|
0: general group\n
|
|
1: vlanbind group\n
|
|
2: portbind group
|
|
@param[in] port_group lan port group
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@note if eth0.x is not exist, set -1;if no need to group, set 0.
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_matrix(int type, int port_group[6]);
|
|
|
|
|
|
/**
|
|
@brief Set switch mirror info
|
|
@param[in] lan2lan mirror configuration
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_lan2lan(ECNT_SWITCHMGR_LAN2LAN lan2lan);
|
|
|
|
/**
|
|
@brief Get switch mirror info
|
|
@param[out] p_lan2lan mirror configuration
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_lan2lan(ECNT_SWITCHMGR_LAN2LAN_INFO *p_lan2lan);
|
|
|
|
/**
|
|
@brief Clear switch mirror configuration
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_clear_lan2lan(void);
|
|
|
|
/**
|
|
@brief Set switch dstq
|
|
@param[in] mode lan dstq mode:\n
|
|
0: disabled\n
|
|
1: down stream forced to gdm1\n
|
|
2: down stream forced to qdma_lan
|
|
@param[in] fc_enable flow control enable/disable
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_dstq(u8 mode, u8 fc_enable);
|
|
|
|
/**
|
|
@brief Set switch global mirror configuration
|
|
@param[in] enable enable/disable mirror
|
|
@param[in] mirror_port mirror destination port
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_mirror_enable(u8 enable, u8 mirror_port);
|
|
|
|
/**
|
|
@brief Set switch port qos enable
|
|
@param[in] port lan port id
|
|
@param[in] enable enable/disable port qos
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_qos(u8 port, u8 enable);
|
|
|
|
/**
|
|
@brief Set switch port qos configuration
|
|
@param[in] port lan port id
|
|
@param[in] qos_param qos configuration(mode, wrr weight..)
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_qos_param(u8 port, ECNT_SWITCHMGR_QOS_CFG qos_param);
|
|
|
|
/**
|
|
@brief Power up/down switch port phy
|
|
@param[in] port lan port id
|
|
@param[in] up 0:power down, other: power up
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_admin(u8 port, u8 up);
|
|
|
|
/**
|
|
@brief Get switch port phy power state
|
|
@param[in] port lan port id
|
|
@param[out] p_up 0:power down, 1: power up
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_admin(u8 port, u8 *p_up);
|
|
|
|
/**
|
|
@brief Set switch port rate limit
|
|
@param[in] port lan port id
|
|
@param[in] dir direction
|
|
@param[in] rate limit speed
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_ratelimit(u8 port, u8 dir, u32 rate);
|
|
|
|
/**
|
|
@brief Get switch port rate limit
|
|
@param[in] port lan port id
|
|
@param[in] dir direction
|
|
@param[out] p_rate limit speed
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_ratelimit(u8 port, u8 dir, u32 *p_rate);
|
|
|
|
/**
|
|
@brief Get switch etherwan port rate limit
|
|
@param[in] dir direction
|
|
@param[out] p_rate limit speed
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_etherwan_port_ratelimit(u32 dir, u32 *rate);
|
|
|
|
/**
|
|
@brief Set switch etherwan port rate limit
|
|
@param[in] rate limit speed
|
|
@param[in] dir direction
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_etherwan_port_ratelimit(u32 rate, u8 dir);
|
|
|
|
/**
|
|
@brief Set switch port phy loopback
|
|
@param[in] port lan port id
|
|
@param[in] enable enable/disable phy loopback
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_loopback(u8 port, u8 enable);
|
|
|
|
/**
|
|
@brief Get switch port phy loopback
|
|
@param[in] port lan port id
|
|
@param[out] p_enable phy loopback state
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_loopback(u8 port, u8 *p_enable);
|
|
|
|
/**
|
|
@brief Set switch port stp state
|
|
@param[in] port lan port id
|
|
@param[in] stp_status STP state
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_stp_status(u8 port, ECNT_SWITCHMGR_STP_STATUS stp_status);
|
|
|
|
/**
|
|
@brief Get switch port stp state
|
|
@param[in] port lan port id
|
|
@param[out] p_stp_status STP state
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_stp_status(u8 port, ECNT_SWITCHMGR_STP_STATUS *p_stp_status);
|
|
|
|
/**
|
|
@brief Get switch port speed mode
|
|
@param[in] port lan port id
|
|
@param[out] p_mode speed mode
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@note The speed mode retrieved by this api only means the configuration set by operator.\n
|
|
The running speed might be different(eg, config:auto-negotiate/running:negotiated speed).
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_speed_mode(u8 port, ECNT_SWITCHMGR_SPEED_MODE *p_mode);
|
|
|
|
/**
|
|
@brief Set switch port speed mode
|
|
@param[in] port lan port id
|
|
@param[out] mode speed mode
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_speed_mode(u8 port, ECNT_SWITCHMGR_SPEED_MODE mode);
|
|
|
|
/**
|
|
@brief Set switch port flow control
|
|
@param[in] port lan port id
|
|
@param[in] enable enable/disable port flow control
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_flow_control(u8 port, u8 enable);
|
|
|
|
/**
|
|
@brief Get switch port flow control
|
|
@param[in] port lan port id
|
|
@param[out] p_enable port flow control state
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_flow_control(u8 port, u8 *p_enable);
|
|
|
|
/**
|
|
@brief Set switch port mac learning limit
|
|
@param[in] port lan port id
|
|
@param[in] cnt number of mac table entries could be learned on the port specified
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_mac_limit(u8 port, u32 cnt);
|
|
|
|
/**
|
|
@brief Get switch port mac learning limit
|
|
@param[in] port lan port id
|
|
@param[out] p_cnt number of mac table entries could be learned on the port specified
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_mac_limit(u8 port, u32 *p_cnt);
|
|
|
|
/**
|
|
@brief Get switch port mac learning num
|
|
@param[in] port lan port id
|
|
@param[out] p_cnt number of mac table entries could be learned on the port specified
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_mac_learn_num(u8 port, u32 *p_cnt);
|
|
|
|
|
|
/**
|
|
@brief Get switch port hardware mac address
|
|
@param[in] port lan port id
|
|
@param[out] mac HW mac address
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_mac(u8 port, u8 mac[6]);
|
|
|
|
/**
|
|
@brief Set switch port learning config
|
|
@param[in] port lan port id
|
|
@param[in] enable enable/disable port learning
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_learning(u8 port, u8 enable);
|
|
|
|
/**
|
|
@brief Get switch port learning config
|
|
@param[in] port lan port id
|
|
@param[in] p_enable port learning config state
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_learning(u8 port, u8 *p_enable);
|
|
|
|
/**
|
|
@brief Set switch port phy max bit rate
|
|
@param[in] port lan port id
|
|
@param[in] speed maximum bit rate, should be "Auto" or "100" or "10"
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_max_bitrate(int port, char* speed);
|
|
|
|
/**
|
|
@brief Get switch port phy max bit rate
|
|
@param[in] port lan port id
|
|
@param[out] speed maximum bit rate, should be "Auto" or "100" or "10"
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_max_bitrate(int port, char* speed);
|
|
|
|
/**
|
|
@brief Set switch port phy duplex
|
|
@param[in] port lan port id
|
|
@param[in] Mode duplex mode, should be "Auto" or "Half" or "Full"
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_duplex(int port, char* Mode);
|
|
|
|
/**
|
|
@brief Get switch port phy duplex
|
|
@param[in] port lan port id
|
|
@param[out] Mode duplex mode, should be "Auto" or "Half" or "Full"
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_duplex(int port, char* Mode);
|
|
|
|
/**
|
|
@brief Set switch port phy auto negotiate config
|
|
@param[in] port lan port id
|
|
@param[in] enable enable/disable auto negotiate
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_autoneg_enable(u8 port, u8 enable);
|
|
|
|
/**
|
|
@brief Get switch port phy auto negotiate config
|
|
@param[in] port lan port id
|
|
@param[out] p_enable enable/disable auto negotiate
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_autoneg_enable(u8 port, u8 *p_enable);
|
|
|
|
/**
|
|
@brief Restart port phy auto negotiate
|
|
@param[in] port lan port id
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_autoneg_restart(u8 port);
|
|
|
|
/**
|
|
@brief Set switch port mirror config
|
|
@param[in] port lan port id
|
|
@param[in] portbased port mirror config
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_mirror(u8 port, ECNT_SWITCHMGR_PORT_MIRROR *portbased);
|
|
|
|
/**
|
|
@brief Set switch port mac transmitting and receiving
|
|
@param[in] port lan port id
|
|
@param[in] direction 0:tx, 1:rx
|
|
@param[in] enable port mirror config
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_mac_txrx(u8 port, u8 direction, u8 enable);
|
|
|
|
/**
|
|
@brief Show switch vlan configuration
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_vlan_disp();
|
|
|
|
/**
|
|
@brief Set switch mac table age time
|
|
@param[in] time age time
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_age_time(u32 time);
|
|
|
|
/**
|
|
@brief Get switch mac table age time
|
|
@param[out] p_time age time
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_age_time( u32 *p_time);
|
|
|
|
/**
|
|
@brief Clear switch mac table
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_clr_mac_table(void);
|
|
|
|
/**
|
|
@brief Clear switch mac table of a specific port
|
|
@param[in] port lan port id
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_clr_port_mac_table(u8 port);
|
|
|
|
/**
|
|
@brief Get switch mac table of a specific port
|
|
@param[in] port lan port id
|
|
@param[out] p_br_table mac table
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_bridge_table(u8 port, ECNT_SWITCHMGR_BRIDGE_TABLE *p_br_table);
|
|
|
|
/**
|
|
@brief Get 16 mac table entries of specific port
|
|
@param[in] port lan port id
|
|
@param[out] mac mac table
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_all_mac(u8 port, ECNT_SWITCHMGR_PORT_ALL_MAC *mac);
|
|
|
|
/**
|
|
@brief Get port by specific mac address
|
|
@param[in] inptr_PortMac mac info
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_by_mac(ECNT_SWITCHMGR_MAC_ENTRY * inptr_PortMac);
|
|
|
|
/**
|
|
@brief Set switch mac table aging
|
|
@param[in] aging_en enable/disable aging
|
|
@param[in] time age time
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_arl_aging(u8 aging_en, u32 time);
|
|
|
|
/**
|
|
@brief Show switch mac table
|
|
@param[in] ac_mat 0: MAC, 1: DIP, 2: SIP
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_arl_mactbldisp(int ac_mat);
|
|
|
|
/**
|
|
@brief Clear switch mac table
|
|
@param[in] ac_mat 0: MAC, 1: DIP, 2: SIP
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_arl_mactblclr(int ac_mat);
|
|
|
|
/**
|
|
@brief Set switch QoS queue mark
|
|
@param[in] enable enable/disable QoS queue mark
|
|
@param[in] shift queue mark shift
|
|
@param[in] width queue mark width
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_queue_mark(u8 enable, u8 shift, u8 width);
|
|
|
|
/**
|
|
@brief Set switch port queue weight
|
|
@param[in] port lan port id
|
|
@param[in] queueId queue id
|
|
@param[in] weight QoS weight
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_port_queue_weight(u8 port, u8 queueId, u8 weight);
|
|
|
|
/**
|
|
@brief Get switch port queue weight
|
|
@param[in] port lan port id
|
|
@param[in] queueId queue id
|
|
@param[out] p_weight QoS weight
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_queue_weight(u8 port, u8 queueId, u8 *p_weight);
|
|
|
|
/**
|
|
@brief Clear switch all port statistics
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_clr_all_port_statistics(void);
|
|
|
|
/**
|
|
@brief Get switch port statistics
|
|
@param[in] port lan port id
|
|
@param[in] p_stats port statistics
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_port_statistics(u8 port, ECNT_SWITCHMGR_PORT_STATISTICS *p_stats);
|
|
|
|
/**
|
|
@brief Set switch storm control port
|
|
@param[in] port lan port id
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_storm_ctrl_port(u16 port);
|
|
|
|
/**
|
|
@brief Set switch port storm control unit
|
|
@param[in] unit storm control unit:\n
|
|
0: 64 packets per second\n
|
|
1: 256 packets per second\n
|
|
2: 1k packets per second\n
|
|
3: 4k packets per second
|
|
@note The switch port to set is specified by ::switchmgr_lib_set_storm_ctrl_port.
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_storm_ctrl_unit(u8 unit);
|
|
|
|
/**
|
|
@brief Set switch port storm control type
|
|
@param[in] type storm control type\n
|
|
1: unknown mac unicast\n
|
|
2: multicast\n
|
|
4: broadcast
|
|
@note The switch port to set is specified by ::switchmgr_lib_set_storm_ctrl_port.
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_storm_ctrl_type(u8 type);
|
|
|
|
/**
|
|
@brief Set switch port storm control mode
|
|
@param[in] mode storm control mode
|
|
@note The switch port to set is specified by ::switchmgr_lib_set_storm_ctrl_port.
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_storm_ctrl_mode(u8 mode);
|
|
|
|
/**
|
|
@brief Set switch port storm control period
|
|
@param[in] period storm control period
|
|
@note The switch port to set is specified by ::switchmgr_lib_set_storm_ctrl_port.
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_storm_ctrl_period(u8 period);
|
|
|
|
/**
|
|
@brief Set internal switch register value
|
|
@param[in] offset register offset
|
|
@param[in] value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_gsww(u32 offset, u32 value);
|
|
|
|
/**
|
|
@brief Get internal switch register value
|
|
@param[in] offset register offset
|
|
@param[out] p_value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_gswr(u32 offset, u32 *p_value);
|
|
|
|
/**
|
|
@brief Set internal/external switch register value
|
|
@param[in] ext_switch indicate internal/external, 0: internal, other: external
|
|
@param[in] reg register offset
|
|
@param[in] value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_gsww2(u32 ext_switch, u32 reg, u32 value);
|
|
|
|
/**
|
|
@brief Get internal/external switch register value
|
|
@param[in] ext_switch indicate internal/external, 0: internal, other: external
|
|
@param[in] reg register offset
|
|
@param[out] p_value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_gswr2(u32 ext_switch, u32 reg, u32 *p_value);
|
|
|
|
/**
|
|
@brief Set internal switch phy register value
|
|
@param[in] phyaddr phy address
|
|
@param[in] reg register address
|
|
@param[in] value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_mii(int phyaddr, int reg, u32 value);
|
|
|
|
/**
|
|
@brief Get internal switch phy register value
|
|
@param[in] phyaddr phy address
|
|
@param[in] reg register address
|
|
@param[out] p_value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_mii(int phyaddr, int reg, u32 *p_value);
|
|
|
|
/**
|
|
@brief Set internal/external switch phy register value
|
|
@param[in] ext_switch indicate internal/external, 0: internal, other: external
|
|
@param[in] phyAddr phy address
|
|
@param[in] reg register address
|
|
@param[in] value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_set_mii2(int ext_switch, int phyAddr, int reg, u32 value);
|
|
|
|
/**
|
|
@brief Get internal/external switch phy register value
|
|
@param[in] ext_switch indicate internal/external, 0: internal, other: external
|
|
@param[in] phyAddr phy address
|
|
@param[in] reg register address
|
|
@param[out] p_value register value
|
|
@return ::ECNT_SWITCHMGR_RET
|
|
@par Supported Chip:
|
|
@code
|
|
EN7512, EN7521, EN7580
|
|
@endcode
|
|
*/
|
|
ECNT_SWITCHMGR_RET switchmgr_lib_get_mii2(int ext_switch, int phyAddr, int reg, u32 *p_value);
|
|
|
|
// ============== redefine =================
|
|
#define ecnt_switchmgr_lib_set_portmap switchmgr_lib_set_portmap
|
|
#define ecnt_switchmgr_lib_set_vlan_active switchmgr_lib_set_vlan_active
|
|
#define ecnt_switchmgr_lib_set_flow_control switchmgr_lib_set_flow_control
|
|
#define ecnt_switchmgr_lib_get_flow_control switchmgr_lib_get_flow_control
|
|
#define ecnt_switchmgr_lib_set_max_framesize switchmgr_lib_set_max_framesize
|
|
#define ecnt_switchmgr_lib_get_max_framesize switchmgr_lib_get_max_framesize
|
|
#define ecnt_switchmgr_lib_set_port_isolate switchmgr_lib_set_port_isolate
|
|
#define ecnt_switchmgr_lib_set_port_matrix switchmgr_lib_set_port_matrix
|
|
#define ecnt_switchmgr_lib_set_lan2lan switchmgr_lib_set_lan2lan
|
|
#define ecnt_switchmgr_lib_get_lan2lan switchmgr_lib_get_lan2lan
|
|
#define ecnt_switchmgr_lib_clear_lan2lan switchmgr_lib_clear_lan2lan
|
|
#define ecnt_switchmgr_lib_set_dstq switchmgr_lib_set_dstq
|
|
#define ecnt_switchmgr_lib_set_mirror_enable switchmgr_lib_set_mirror_enable
|
|
#define ecnt_switchmgr_lib_set_port_qos switchmgr_lib_set_port_qos
|
|
#define ecnt_switchmgr_lib_set_port_qos_param switchmgr_lib_set_port_qos_param
|
|
#define ecnt_switchmgr_lib_set_port_admin switchmgr_lib_set_port_admin
|
|
#define ecnt_switchmgr_lib_get_port_admin switchmgr_lib_get_port_admin
|
|
#define ecnt_switchmgr_lib_set_port_ratelimit switchmgr_lib_set_port_ratelimit
|
|
#define ecnt_switchmgr_lib_get_port_ratelimit switchmgr_lib_get_port_ratelimit
|
|
#define ecnt_switchmgr_lib_set_port_loopback switchmgr_lib_set_port_loopback
|
|
#define ecnt_switchmgr_lib_get_port_loopback switchmgr_lib_get_port_loopback
|
|
#define ecnt_switchmgr_lib_set_port_stp_status switchmgr_lib_set_port_stp_status
|
|
#define ecnt_switchmgr_lib_get_port_stp_status switchmgr_lib_get_port_stp_status
|
|
#define ecnt_switchmgr_lib_get_port_speed_mode switchmgr_lib_get_port_speed_mode
|
|
#define ecnt_switchmgr_lib_set_port_flow_control switchmgr_lib_set_port_flow_control
|
|
#define ecnt_switchmgr_lib_get_port_flow_control switchmgr_lib_get_port_flow_control
|
|
#define ecnt_switchmgr_lib_set_port_mac_limit switchmgr_lib_set_port_mac_limit
|
|
#define ecnt_switchmgr_lib_get_port_mac_limit switchmgr_lib_get_port_mac_limit
|
|
#define ecnt_switchmgr_lib_get_port_mac switchmgr_lib_get_port_mac
|
|
#define ecnt_switchmgr_lib_set_port_learning switchmgr_lib_set_port_learning
|
|
#define ecnt_switchmgr_lib_get_port_learning switchmgr_lib_get_port_learning
|
|
#define ecnt_switchmgr_lib_set_port_max_bitrate switchmgr_lib_set_port_max_bitrate
|
|
#define ecnt_switchmgr_lib_get_port_max_bitrate switchmgr_lib_get_port_max_bitrate
|
|
#define ecnt_switchmgr_lib_set_port_duplex switchmgr_lib_set_port_duplex
|
|
#define ecnt_switchmgr_lib_get_port_duplex switchmgr_lib_get_port_duplex
|
|
#define ecnt_switchmgr_lib_set_port_autoneg_enable switchmgr_lib_set_port_autoneg_enable
|
|
#define ecnt_switchmgr_lib_get_port_autoneg_enable switchmgr_lib_get_port_autoneg_enable
|
|
#define ecnt_switchmgr_lib_set_port_autoneg_restart switchmgr_lib_set_port_autoneg_restart
|
|
#define ecnt_switchmgr_lib_set_port_mirror switchmgr_lib_set_port_mirror
|
|
#define ecnt_switchmgr_lib_set_port_mac_txrx switchmgr_lib_set_port_mac_txrx
|
|
#define ecnt_switchmgr_lib_set_vlan_disp switchmgr_lib_set_vlan_disp
|
|
#define ecnt_switchmgr_lib_set_age_time switchmgr_lib_set_age_time
|
|
#define ecnt_switchmgr_lib_get_age_time switchmgr_lib_get_age_time
|
|
#define ecnt_switchmgr_lib_clr_mac_table switchmgr_lib_clr_mac_table
|
|
#define ecnt_switchmgr_lib_clr_port_mac_table switchmgr_lib_clr_port_mac_table
|
|
#define ecnt_switchmgr_lib_get_port_bridge_table switchmgr_lib_get_port_bridge_table
|
|
#define ecnt_switchmgr_lib_get_port_all_mac switchmgr_lib_get_port_all_mac
|
|
#define ecnt_switchmgr_lib_set_arl_aging switchmgr_lib_set_arl_aging
|
|
#define ecnt_switchmgr_lib_set_arl_mactbldisp switchmgr_lib_set_arl_mactbldisp
|
|
#define ecnt_switchmgr_lib_set_arl_mactblclr switchmgr_lib_set_arl_mactblclr
|
|
#define ecnt_switchmgr_lib_set_queue_mark switchmgr_lib_set_queue_mark
|
|
#define ecnt_switchmgr_lib_set_port_queue_weight switchmgr_lib_set_port_queue_weight
|
|
#define ecnt_switchmgr_lib_get_port_queue_weight switchmgr_lib_get_port_queue_weight
|
|
#define ecnt_switchmgr_lib_clr_all_port_statistics switchmgr_lib_clr_all_port_statistics
|
|
#define ecnt_switchmgr_lib_get_port_statistics switchmgr_lib_get_port_statistics
|
|
#define ecnt_switchmgr_lib_set_storm_ctrl_port switchmgr_lib_set_storm_ctrl_port
|
|
#define ecnt_switchmgr_lib_set_storm_ctrl_unit switchmgr_lib_set_storm_ctrl_unit
|
|
#define ecnt_switchmgr_lib_set_storm_ctrl_type switchmgr_lib_set_storm_ctrl_type
|
|
#define ecnt_switchmgr_lib_set_storm_ctrl_mode switchmgr_lib_set_storm_ctrl_mode
|
|
#define ecnt_switchmgr_lib_set_storm_ctrl_period switchmgr_lib_set_storm_ctrl_period
|
|
#define ecnt_switchmgr_lib_set_gsww switchmgr_lib_set_gsww
|
|
#define ecnt_switchmgr_lib_get_gswr switchmgr_lib_get_gswr
|
|
#define ecnt_switchmgr_lib_set_gsww2 switchmgr_lib_set_gsww2
|
|
#define ecnt_switchmgr_lib_get_gswr2 switchmgr_lib_get_gswr2
|
|
#define ecnt_switchmgr_lib_set_mii switchmgr_lib_set_mii
|
|
#define ecnt_switchmgr_lib_get_mii switchmgr_lib_get_mii
|
|
#define ecnt_switchmgr_lib_set_mii2 switchmgr_lib_set_mii2
|
|
#define ecnt_switchmgr_lib_get_mii2 switchmgr_lib_get_mii2
|
|
|
|
//added new
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#define ecnt_switchmgr_lib_get_chip_type switchmgr_lib_get_chip_type
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#define ecnt_switchmgr_lib_get_port_link_state switchmgr_lib_get_port_link_state
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#define ecnt_switchmgr_lib_set_port_link_state switchmgr_lib_set_port_link_state
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#define ecnt_switchmgr_lib_set_eth_general_api switchmgr_lib_set_eth_general_api
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#define ecnt_switchmgr_lib_set_acl_upstream_notunicast_ratelimit switchmgr_lib_set_acl_upstream_notunicast_ratelimit
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#define ecnt_switchmgr_lib_set_acl_upstream_vlan_ratelimit switchmgr_lib_set_acl_upstream_vlan_ratelimit
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#define ecnt_switchmgr_lib_set_port_speed_mode switchmgr_lib_set_port_speed_mode
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#define ecnt_switchmgr_lib_get_port_configuration_status switchmgr_lib_get_port_configuration_status
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#define ecnt_switchmgr_lib_set_mac_match_acl switchmgr_lib_set_mac_match_acl
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#endif /* _API_LIB_SWITCHMGR_H */
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