forked from dlink-dir_819/openwrt
6b99c5d21e
Backport GIC ITS support for RK356x SoC, which fixes long-standing MSI/MSI-X bug. (Previously MSI-X could only work on one PCIe node) e.g. [ 7.250882] r8125 0002:01:00.0: no MSI/MSI-X. Back to INTx. Tested on Radxa E25 with kmod-r8125-rss driver. Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/18800 Signed-off-by: Robert Marko <robimarko@gmail.com>
55 lines
1.9 KiB
Diff
55 lines
1.9 KiB
Diff
From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Sat, 8 Mar 2025 17:30:08 +0800
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Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
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Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move
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PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
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MSI on rk3568 to use ITS, so that all MSI-X can work properly.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -64,7 +64,7 @@
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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- bus-range = <0x0 0xf>;
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+ bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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@@ -87,7 +87,7 @@
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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- msi-map = <0x0 &gic 0x1000 0x1000>;
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+ msi-map = <0x1000 &its 0x1000 0x1000>;
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num-lanes = <1>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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@@ -117,7 +117,7 @@
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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- bus-range = <0x0 0xf>;
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+ bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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@@ -140,7 +140,7 @@
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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- msi-map = <0x0 &gic 0x2000 0x1000>;
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+ msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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