forked from dlink-dir_819/openwrt
1308b4fb1c
Some DTS files have a qsgmii link mode for the CPU port. This does not harm but it is wrong. The CPU port of the realtek switch is always directly connected to the switch by some unknown wiring and should therefore be described as internal. Align the wrongly defined DTS files to the standard. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/18691 Signed-off-by: Robert Marko <robimarko@gmail.com>
324 lines
6.2 KiB
Plaintext
324 lines
6.2 KiB
Plaintext
/dts-v1/;
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#include "rtl839x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
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model = "Zyxel GS1900-48";
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_sys: sys {
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label = "green:sys";
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <100>;
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};
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};
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/* i2c of the left SFP cage: port 49 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of the right SFP cage: port 50 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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};
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};
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&mdio_aux {
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status = "okay";
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gpio1: expander@3 {
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compatible = "realtek,rtl8231";
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reg = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio1 0 0 37>;
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led-controller {
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compatible = "realtek,rtl8231-leds";
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status = "disabled";
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "u-boot-env2";
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reg = <0x50000 0x10000>;
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read-only;
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};
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partition@60000 {
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label = "jffs";
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reg = <0x60000 0x100000>;
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};
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partition@160000 {
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label = "jffs2";
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reg = <0x160000 0x100000>;
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};
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partition@260000 {
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label = "firmware";
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reg = <0x260000 0xda0000>;
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,ih-magic = <0x83800000>;
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* External phy RTL8218B #1 */
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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/* External phy RTL8218B #2 */
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EXTERNAL_PHY(8)
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EXTERNAL_PHY(9)
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EXTERNAL_PHY(10)
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EXTERNAL_PHY(11)
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EXTERNAL_PHY(12)
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EXTERNAL_PHY(13)
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EXTERNAL_PHY(14)
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EXTERNAL_PHY(15)
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/* External phy RTL8218B #3 */
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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/* External phy RTL8218B #4 */
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EXTERNAL_PHY(24)
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EXTERNAL_PHY(25)
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EXTERNAL_PHY(26)
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EXTERNAL_PHY(27)
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EXTERNAL_PHY(28)
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EXTERNAL_PHY(29)
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EXTERNAL_PHY(30)
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EXTERNAL_PHY(31)
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/* External phy RTL8218B #5 */
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EXTERNAL_PHY(32)
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EXTERNAL_PHY(33)
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EXTERNAL_PHY(34)
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EXTERNAL_PHY(35)
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EXTERNAL_PHY(36)
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EXTERNAL_PHY(37)
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EXTERNAL_PHY(38)
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EXTERNAL_PHY(39)
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/* External phy RTL8218B #6 */
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EXTERNAL_PHY(40)
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EXTERNAL_PHY(41)
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EXTERNAL_PHY(42)
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EXTERNAL_PHY(43)
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EXTERNAL_PHY(44)
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EXTERNAL_PHY(45)
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EXTERNAL_PHY(46)
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EXTERNAL_PHY(47)
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/* RTL8393 Internal SerDes */
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INTERNAL_PHY(48)
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INTERNAL_PHY(49)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 01, qsgmii)
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SWITCH_PORT(1, 02, qsgmii)
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SWITCH_PORT(2, 03, qsgmii)
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SWITCH_PORT(3, 04, qsgmii)
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SWITCH_PORT(4, 05, qsgmii)
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SWITCH_PORT(5, 06, qsgmii)
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SWITCH_PORT(6, 07, qsgmii)
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SWITCH_PORT(7, 08, qsgmii)
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SWITCH_PORT(8, 09, qsgmii)
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SWITCH_PORT(9, 10, qsgmii)
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SWITCH_PORT(10, 11, qsgmii)
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SWITCH_PORT(11, 12, qsgmii)
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SWITCH_PORT(12, 13, qsgmii)
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SWITCH_PORT(13, 14, qsgmii)
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SWITCH_PORT(14, 15, qsgmii)
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SWITCH_PORT(15, 16, qsgmii)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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SWITCH_PORT(24, 25, qsgmii)
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SWITCH_PORT(25, 26, qsgmii)
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SWITCH_PORT(26, 27, qsgmii)
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SWITCH_PORT(27, 28, qsgmii)
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SWITCH_PORT(28, 29, qsgmii)
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SWITCH_PORT(29, 30, qsgmii)
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SWITCH_PORT(30, 31, qsgmii)
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SWITCH_PORT(31, 32, qsgmii)
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SWITCH_PORT(32, 33, qsgmii)
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SWITCH_PORT(33, 34, qsgmii)
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SWITCH_PORT(34, 35, qsgmii)
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SWITCH_PORT(35, 36, qsgmii)
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SWITCH_PORT(36, 37, qsgmii)
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SWITCH_PORT(37, 38, qsgmii)
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SWITCH_PORT(38, 39, qsgmii)
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SWITCH_PORT(39, 40, qsgmii)
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SWITCH_PORT(40, 41, qsgmii)
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SWITCH_PORT(41, 42, qsgmii)
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SWITCH_PORT(42, 43, qsgmii)
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SWITCH_PORT(43, 44, qsgmii)
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SWITCH_PORT(44, 45, qsgmii)
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SWITCH_PORT(45, 46, qsgmii)
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SWITCH_PORT(46, 47, qsgmii)
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SWITCH_PORT(47, 48, qsgmii)
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/* SFP cages */
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port@48 {
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reg = <48>;
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label = "lan49";
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phy-mode = "sgmii";
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phy-handle = <&phy48>;
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sfp = <&sfp0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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port@49 {
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reg = <49>;
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label = "lan50";
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phy-mode = "sgmii";
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phy-handle = <&phy49>;
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sfp = <&sfp1>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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/* CPU-Port */
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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