forked from dlink-dir_819/openwrt
d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
135 lines
3.3 KiB
Diff
135 lines
3.3 KiB
Diff
From 28682ca027b9fa64f3de4cea99373642f36c4e6c Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 8 Aug 2021 19:32:14 -0500
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Subject: [PATCH 80/90] gpio: sunxi: Hack up the driver for the D1
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm/include/asm/arch-sunxi/gpio.h | 12 ++++++++++--
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arch/arm/mach-sunxi/pinmux.c | 8 +++++++-
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drivers/gpio/sunxi_gpio.c | 3 +++
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3 files changed, 20 insertions(+), 3 deletions(-)
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--- a/arch/arm/include/asm/arch-sunxi/gpio.h
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+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
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@@ -9,7 +9,9 @@
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#define _SUNXI_GPIO_H
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#include <linux/types.h>
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+#if 0
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#include <asm/arch/cpu.h>
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+#endif
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/*
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* sunxi has 9 banks of gpio, they are:
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@@ -55,30 +57,36 @@
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struct sunxi_gpio {
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u32 cfg[4];
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u32 dat;
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- u32 drv[2];
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+ u32 drv[4];
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u32 pull[2];
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+ u32 reserved;
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};
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/* gpio interrupt control */
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struct sunxi_gpio_int {
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- u32 cfg[3];
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+ u32 cfg[4];
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u32 ctl;
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u32 sta;
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u32 deb; /* interrupt debounce */
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+ u32 reserved;
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};
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+#if 0
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struct sunxi_gpio_reg {
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struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
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u8 res[0xbc];
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struct sunxi_gpio_int gpio_int;
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};
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+#endif
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#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
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#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
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+#if 0
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#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
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&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
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&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
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+#endif
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#define GPIO_BANK(pin) ((pin) >> 5)
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#define GPIO_NUM(pin) ((pin) & 0x1f)
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--- a/arch/arm/mach-sunxi/pinmux.c
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+++ b/arch/arm/mach-sunxi/pinmux.c
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@@ -7,7 +7,7 @@
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#include <common.h>
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#include <asm/io.h>
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-#include <asm/arch/gpio.h>
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+//#include <asm/arch/gpio.h>
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void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
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{
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@@ -17,6 +17,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi
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clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
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}
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+#if !CONFIG_IS_ENABLED(DM_GPIO)
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void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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@@ -24,6 +25,7 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32
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sunxi_gpio_set_cfgbank(pio, pin, val);
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}
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+#endif
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int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
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{
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@@ -37,6 +39,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_
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return cfg & 0xf;
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}
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+#if !CONFIG_IS_ENABLED(DM_GPIO)
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int sunxi_gpio_get_cfgpin(u32 pin)
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{
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u32 bank = GPIO_BANK(pin);
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@@ -52,6 +55,7 @@ void sunxi_gpio_set_drv(u32 pin, u32 val
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sunxi_gpio_set_drv_bank(pio, pin, val);
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}
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+#endif
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void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
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{
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@@ -61,6 +65,7 @@ void sunxi_gpio_set_drv_bank(struct sunx
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clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
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}
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+#if !CONFIG_IS_ENABLED(DM_GPIO)
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void sunxi_gpio_set_pull(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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@@ -68,6 +73,7 @@ void sunxi_gpio_set_pull(u32 pin, u32 va
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sunxi_gpio_set_pull_bank(pio, pin, val);
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}
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+#endif
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void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
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{
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--- a/drivers/gpio/sunxi_gpio.c
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+++ b/drivers/gpio/sunxi_gpio.c
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@@ -18,6 +18,9 @@
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#include <asm/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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+#include "../../arch/arm/include/asm/arch-sunxi/gpio.h"
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+#include "../../arch/arm/mach-sunxi/pinmux.c"
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+
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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static int sunxi_gpio_output(u32 pin, u32 val)
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{
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