forked from dlink-dir_819/openwrt
d41d9befb9
Add u-boot bootloader based on 2023.01 to support D1-based boards, currently: - Dongshan Nezha STU - LicheePi RV Dock - MangoPi MQ-Pro - Nezha D1 Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
101 lines
3.1 KiB
Diff
101 lines
3.1 KiB
Diff
From 9766169812418aee10dbc8d40aca27c1c576f521 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Thu, 14 Jul 2022 23:39:46 -0500
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Subject: [PATCH 15/90] net: sun8i-emac: Use common syscon setup for R40
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While R40 puts the EMAC syscon register at a different address from
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other variants, the relevant portion of the register's layout is the
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same. Factor out the register offset so the same code can be shared
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by all variants. This matches what the Linux driver does.
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This change provides two benefits beyond the simplification:
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- R40 boards now respect the RX delays from the devicetree
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- This resolves a warning on architectures where readl/writel
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expect the address to have a pointer type, not phys_addr_t.
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Series-to: sunxi
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Cover-letter:
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net: sun8i-emac: Allwinner D1 Support
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D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
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However, there are a couple of issues with the driver preventing it
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being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
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a general cleanup.
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END
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/net/sun8i_emac.c | 29 ++++++++++++-----------------
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1 file changed, 12 insertions(+), 17 deletions(-)
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--- a/drivers/net/sun8i_emac.c
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+++ b/drivers/net/sun8i_emac.c
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@@ -162,7 +162,7 @@ struct emac_eth_dev {
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enum emac_variant variant;
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void *mac_reg;
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- phys_addr_t sysctl_reg;
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+ void *sysctl_reg;
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struct phy_device *phydev;
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struct mii_dev *bus;
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struct clk tx_clk;
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@@ -317,18 +317,7 @@ static int sun8i_emac_set_syscon(struct
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{
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u32 reg;
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- if (priv->variant == R40_GMAC) {
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- /* Select RGMII for R40 */
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- reg = readl(priv->sysctl_reg + 0x164);
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- reg |= SC_ETCS_INT_GMII |
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- SC_EPIT |
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- (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
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-
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- writel(reg, priv->sysctl_reg + 0x164);
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- return 0;
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- }
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-
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- reg = readl(priv->sysctl_reg + 0x30);
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+ reg = readl(priv->sysctl_reg);
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reg = sun8i_emac_set_syscon_ephy(priv, reg);
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@@ -369,7 +358,7 @@ static int sun8i_emac_set_syscon(struct
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reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
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& SC_ERXDC_MASK;
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- writel(reg, priv->sysctl_reg + 0x30);
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+ writel(reg, priv->sysctl_reg);
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return 0;
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}
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@@ -792,6 +781,7 @@ static int sun8i_emac_eth_of_to_plat(str
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struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
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struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
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struct emac_eth_dev *priv = dev_get_priv(dev);
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+ phys_addr_t syscon_base;
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const fdt32_t *reg;
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int node = dev_of_offset(dev);
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int offset = 0;
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@@ -837,13 +827,18 @@ static int sun8i_emac_eth_of_to_plat(str
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__func__);
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return -EINVAL;
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}
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- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
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- offset, reg);
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- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
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+
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+ syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
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+ if (syscon_base == FDT_ADDR_T_NONE) {
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debug("%s: Cannot find syscon base address\n", __func__);
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return -EINVAL;
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}
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+ if (priv->variant == R40_GMAC)
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+ priv->sysctl_reg = (void *)syscon_base + 0x164;
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+ else
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+ priv->sysctl_reg = (void *)syscon_base + 0x30;
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+
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pdata->phy_interface = -1;
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priv->phyaddr = -1;
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priv->use_internal_phy = false;
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