openwrt/target/linux/mediatek/dts/mt7981b-wavlink-wl-3port-128nand-common.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/dts-v1/;

#include <dt-bindings/pinctrl/mt65xx.h>

#include "mt7981b.dtsi"

/ {
	chosen {
		stdout-path = "serial0:115200n8";
	};

	gpio-keys {
		compatible = "gpio-keys";

		button-reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
		};
	};
};

&uart0 {
	status = "okay";
};

&watchdog {
	status = "okay";
};

&pio {
	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};

		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
		};

		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
		};
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "spi-nand";
		reg = <0>;

		spi-max-frequency = <52000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x0 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x100000 0x80000>;
				read-only;
			};

			factory: partition@180000 {
				label = "factory";
				reg = <0x180000 0x200000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;
					
					eeprom_factory: eeprom@0 {
						reg = <0x0 0x1000>;
					};					

					macaddr_factory_4: macaddr@4 {
						reg = <0x4 0x6>;
					};
				};
			};

			partition@380000 {
				label = "fip";
				reg = <0x380000 0x200000>;
				read-only;
			};

			partition@580000 {
				label = "ubi";
				reg = <0x580000 0x4000000>;
			};

			partition@4580000 {
				label = "hw";
				reg = <0x4580000 0x80000>;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					macaddr_hw_44e: macaddr@44e {
						compatible = "mac-base";
						reg = <0x44e 0x11>;
						#nvmem-cell-cells = <1>;
					};
				};
			};
		};
	};
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		nvmem-cell-names = "mac-address";
		nvmem-cells = <&macaddr_hw_44e 0>;

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "gmii";
		phy-handle = <&int_gbe_phy>;

		nvmem-cell-names = "mac-address";
		nvmem-cells = <&macaddr_hw_44e 1>;
	};
};

&mdio_bus {
	switch: switch@1f {
		compatible = "mediatek,mt7531";
		reg = <31>;
		reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;
			label = "lan2";
		};

		port@2 {
			reg = <2>;
			label = "lan1";
		};

		port@6 {
			reg = <6>;
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&wifi {
	status = "okay";
	nvmem-cells = <&eeprom_factory 0>;
	nvmem-cell-names = "eeprom";
};