forked from Openwrt/openwrt
6f33529a12
Add the missing "device_type" property to fix the memory node. The Linux kernel can not get the memory size without it. Though u-boot can automatically fixup the memory node by adding the "device_type" and "reg" properties if the CONFIG_ARCH_FIXUP_FDT_MEMORY symbol is enabled, it's better not to rely on this optional feature. This patch also adds the reg address for the memory node name to follow the naming rules. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/19741 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
460 lines
7.7 KiB
Plaintext
460 lines
7.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "mt7981b.dtsi"
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/ {
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model = "GatoNetworks GDSP";
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compatible = "gatonetworks,gdsp", "mediatek,mt7981";
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aliases {
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serial0 = &uart0;
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label-mac-device = &wifi_band_0;
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led-boot = &sg1;
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led-failsafe = &sg1;
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led-running = &sg1;
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led-upgrade = &sg1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=ttyS0,115200n1 earlycon=uart8250,mmio32,0x11002000";
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rootdisk = <&firmware>;
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};
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memory@40000000 {
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reg = <0 0x40000000 0 0x10000000>;
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device_type = "memory";
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-export {
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compatible = "gpio-export";
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modem1 {
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gpio-export,name = "modem1";
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gpio-export,output = <0>;
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gpios = <&pio 2 GPIO_ACTIVE_LOW>;
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};
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modem2 {
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gpio-export,name = "modem2";
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gpio-export,output = <0>;
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gpios = <&pio 14 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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sim1 {
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label = "green:sim1";
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gpios = <&pio 13 GPIO_ACTIVE_LOW>;
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};
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sim2 {
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label = "green:sim2";
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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sg1: sg1 {
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label = "green:sg1";
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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sg2 {
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label = "green:sg2";
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gpios = <&pio 11 GPIO_ACTIVE_LOW>;
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};
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sg3 {
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label = "green:sg3";
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gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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};
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sg4 {
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label = "green:sg4";
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gpios = <&pio 7 GPIO_ACTIVE_LOW>;
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};
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sg5 {
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label = "green:sg5";
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gpios = <&pio 8 GPIO_ACTIVE_LOW>;
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};
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sg6 {
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label = "green:sg6";
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-watchdog {
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compatible = "linux,wdt-gpio";
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gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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hw_algo = "toggle";
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hw_margin_ms = <25000>;
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always-running;
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};
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};
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&watchdog {
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status = "okay";
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};
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&mmc0 {
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "state_uhs";
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pinctrl-0 = <&mmc0_pins_default>;
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pinctrl-1 = <&mmc0_pins_uhs>;
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bus-width = <4>;
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max-frequency = <50000000>;
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cap-sd-highspeed;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_3p3v>;
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no-mmc;
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no-sdio;
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cells = <&macaddr_lan>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 39 0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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swphy0: phy@0 {
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reg = <0>;
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};
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swphy1: phy@1 {
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reg = <1>;
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};
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swphy2: phy@2 {
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reg = <2>;
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};
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swphy3: phy@3 {
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reg = <3>;
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};
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swphy4: phy@4 {
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reg = <4>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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phy-handle = <&swphy0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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phy-handle = <&swphy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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phy-handle = <&swphy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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phy-handle = <&swphy3>;
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};
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port@4 {
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reg = <4>;
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label = "wan";
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nvmem-cells = <&macaddr_wan>;
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nvmem-cell-names = "mac-address";
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phy-handle = <&swphy4>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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&crypto {
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status = "okay";
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};
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&wifi {
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#address-cells = <1>;
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#size-cells = <0>;
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mediatek,mtd-eeprom = <&factory 0x0>;
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status = "okay";
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wifi_band_0: band@0 {
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reg = <0>;
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nvmem-cells = <&macaddr_wifi 0>;
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nvmem-cell-names = "mac-address";
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};
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band@1 {
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reg = <1>;
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nvmem-cells = <&macaddr_wifi 1>;
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nvmem-cell-names = "mac-address";
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};
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};
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&spi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi2_flash_pins>;
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status = "okay";
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <52000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "BL2";
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reg = <0x00000 0x0040000>;
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read-only;
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};
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partition@40000 {
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label = "u-boot-env";
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reg = <0x40000 0x0010000>;
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};
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factory: partition@50000 {
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label = "Factory";
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reg = <0x50000 0x00B0000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_wifi: macaddr@4 {
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reg = <0x4 0x6>;
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compatible = "mac-base";
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#nvmem-cell-cells = <1>;
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};
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macaddr_wan: macaddr@24 {
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reg = <0x24 0x6>;
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};
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macaddr_lan: macaddr@2a {
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reg = <0x2a 0x6>;
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};
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};
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};
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partition@100000 {
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label = "FIP";
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reg = <0x100000 0x0080000>;
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read-only;
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};
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firmware: partition@180000 {
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label = "firmware";
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reg = <0x180000 0x1E80000>;
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};
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};
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};
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};
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&pio {
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uart1_pins: uart1-pins {
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mux {
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function = "uart";
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groups = "uart1_0";
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};
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};
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mmc0_pins_default: mmc0-pins-default {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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conf-cmd-dat {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
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"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
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"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
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input-enable;
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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conf-clk {
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pins = "SPI1_CS";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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conf-rst {
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pins = "PWM0";
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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mmc0_pins_uhs: mmc0-pins-uhs {
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mux {
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function = "flash";
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groups = "emmc_45";
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};
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conf-cmd-dat {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
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"SPI0_CS", "SPI0_HOLD", "SPI0_WP",
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"SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
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input-enable;
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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conf-clk {
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pins = "SPI1_CS";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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conf-rst {
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pins = "PWM0";
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drive-strength = <MTK_DRIVE_4mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2_0_tx_rx";
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};
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};
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spi2_flash_pins: spi2-pins {
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mux {
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function = "spi";
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groups = "spi2", "spi2_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "disabled";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&usb_phy {
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status = "okay";
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};
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&xhci {
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mediatek,u3p-dis-msk = <0x0>;
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>;
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status = "okay";
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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};
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