openwrt/target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

#include "mt7622.dtsi"
#include "mt6380.dtsi"

/ {
	aliases {
		ethernet0 = &gmac0;
		label-mac-device = &gmac0;
		led-boot = &led_system;
		led-failsafe = &led_system;
		led-running = &led_system;
		led-upgrade = &led_system;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n1";
		bootargs = "console=ttyS0,115200n1 swiotlb=512";
	};

	cpus {
		cpu@0 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};

		cpu@1 {
			proc-supply = <&mt6380_vcpu_reg>;
			sram-supply = <&mt6380_vm_reg>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 102 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		mesh_green {
			label = "green:mesh";
			gpios = <&pio 79 GPIO_ACTIVE_LOW>;
		};

		mesh_red {
			label = "red:mesh";
			gpios = <&pio 82 GPIO_ACTIVE_LOW>;
		};

		led_system: system_blue {
			label = "blue:system";
			gpios = <&pio 81 GPIO_ACTIVE_LOW>;
			default-state = "on";
		};
	};

	memory@40000000 {
		reg = <0 0x40000000 0 0x40000000>;
		device_type = "memory";
	};
};

&eth {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&eth_pins>;

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-connection-type = "2500base-x";
		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		switch@1f {
			compatible = "mediatek,mt7531";
			reg = <31>;
			reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&pio>;
			interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan1";
				};

				port@1 {
					reg = <1>;
					label = "lan2";
				};

				port@2 {
					reg = <2>;
					label = "lan3";
				};

				port@3 {
					reg = <3>;
					label = "lan4";
				};

				wan: port@4 {
					reg = <4>;
					label = "wan";
				};

				port@6 {
					reg = <6>;
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};
	};
};

&pcie0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pcie0_pins>;
};

&pio {
	epa_elna_pins: epa-elna-pins {
		mux {
			function = "antsel";
			groups = "antsel0", "antsel1", "antsel2", "antsel3",
				"antsel4", "antsel5", "antsel6", "antsel7",
				"antsel8", "antsel9", "antsel12", "antsel13",
				"antsel14", "antsel15", "antsel16", "antsel17";
		};
	};

	eth_pins: eth-pins {
		mux {
			function = "eth";
			groups = "mdc_mdio", "rgmii_via_gmac2";
		};
	};

	pcie0_pins: pcie0-pins {
		mux {
			function = "pcie";
			groups = "pcie0_pad_perst",
				 "pcie0_0_waken",
				 "pcie0_0_clkreq";
		};
	};

	pmic_bus_pins: pmic-bus-pins {
		mux {
			function = "pmic";
			groups = "pmic_bus";
		};
	};

	spi_nor_pins: spi-nor-pins {
		mux {
			function = "flash";
			groups = "spi_nor";
		};
	};

	uart0_pins: uart0-pins {
		mux {
			function = "uart";
			groups = "uart0_0_tx_rx";
		};
	};

	watchdog_pins: watchdog-pins {
		mux {
			function = "watchdog";
			groups = "watchdog";
		};
	};
};

&pwrap {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&pmic_bus_pins>;
};

&rtc {
	status = "disabled";
};

&uart0 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;
};

&watchdog {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&watchdog_pins>;
};