forked from Openwrt/openwrt
230c6f44ab
Remove upstreamed: 004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch [1] 709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch [2] Manually rebased: 422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch 701-net-dsa-add-out-of-band-tagging-protocol.patch 850-soc-add-qualcomm-syscon.patch 900-PCI-qcom-add-hack-compatible-for-ipq4019-Lantiq-DSL.patch 910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-6.12.y&id=ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-6.12.y&id=2338f4315f16b937e924ff679b91bb8c0ab53f25 Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18725 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
79 lines
2.9 KiB
Diff
79 lines
2.9 KiB
Diff
From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Date: Fri, 4 Nov 2022 18:41:51 +0100
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
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Ethernet controller
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The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
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connected to the CPU through the internal IPQESS Ethernet controller.
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Add support for this internal interface, which is internally connected to a
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modified version of the QCA8K Ethernet switch.
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This Ethernet controller only support a specific internal interface mode
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for connection to the switch.
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Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
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1 file changed, 48 insertions(+)
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--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
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@@ -600,6 +600,54 @@
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status = "disabled";
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};
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+ gmac: ethernet@c080000 {
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+ compatible = "qcom,ipq4019-ess-edma";
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+ reg = <0xc080000 0x8000>;
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+ resets = <&gcc ESS_RESET>;
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+ reset-names = "ess";
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+ clocks = <&gcc GCC_ESS_CLK>;
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+ clock-names = "ess";
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+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
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+ phy-mode = "internal";
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+ status = "disabled";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+
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mdio: mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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