forked from Openwrt/openwrt
83648084cc
Reorganize backported 6.12 generic patches, grouping them by following a standard naming XXX-XX-v6.x-patch-file-name.patch. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
60 lines
2.4 KiB
Diff
60 lines
2.4 KiB
Diff
From bc1a65eb81a21e2aa3c3dca058ee8adf687b6ef5 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Mon, 2 Jun 2025 21:39:53 +0200
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Subject: [PATCH] net: dsa: b53: do not touch DLL_IQQD on bcm53115
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According to OpenMDK, bit 2 of the RGMII register has a different
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meaning for BCM53115 [1]:
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"DLL_IQQD 1: In the IDDQ mode, power is down0: Normal function
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mode"
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Configuring RGMII delay works without setting this bit, so let's keep it
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at the default. For other chips, we always set it, so not clearing it
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is not an issue.
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One would assume BCM53118 works the same, but OpenMDK is not quite sure
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what this bit actually means [2]:
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"BYPASS_IMP_2NS_DEL #1: In the IDDQ mode, power is down#0: Normal
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function mode1: Bypass dll65_2ns_del IP0: Use
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dll65_2ns_del IP"
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So lets keep setting it for now.
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[1] https://github.com/Broadcom-Network-Switching-Software/OpenMDK/blob/master/cdk/PKG/chip/bcm53115/bcm53115_a0_defs.h#L19871
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[2] https://github.com/Broadcom-Network-Switching-Software/OpenMDK/blob/master/cdk/PKG/chip/bcm53118/bcm53118_a0_defs.h#L14392
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Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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Link: https://patch.msgid.link/20250602193953.1010487-6-jonas.gorski@gmail.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/b53/b53_common.c | 8 +++++---
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1 file changed, 5 insertions(+), 3 deletions(-)
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--- a/drivers/net/dsa/b53/b53_common.c
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+++ b/drivers/net/dsa/b53/b53_common.c
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@@ -1354,8 +1354,7 @@ static void b53_adjust_531x5_rgmii(struc
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* tx_clk aligned timing (restoring to reset defaults)
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*/
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b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
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- rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
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- RGMII_CTRL_TIMING_SEL);
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+ rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
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/* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
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* sure that we enable the port TX clock internal delay to
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@@ -1375,7 +1374,10 @@ static void b53_adjust_531x5_rgmii(struc
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rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
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if (interface == PHY_INTERFACE_MODE_RGMII)
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rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
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- rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
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+
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+ if (dev->chip_id != BCM53115_DEVICE_ID)
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+ rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
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+
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b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
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dev_info(ds->dev, "Configured port %d for %s\n", port,
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