149 lines
5.4 KiB
C
149 lines
5.4 KiB
C
/*
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<:label-BRCM:2012:DUAL/GPL:standard
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and
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to copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Not withstanding the above, under no circumstances may you combine
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this software in any way with any other Broadcom software provided
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under a license other than the GPL, without Broadcom's express prior
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written consent.
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:>
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*/
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#ifndef BCMPCI_H
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#define BCMPCI_H
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/* BUS assignment */
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#define BCM_BUS_PCI 0 /* bus 0, MPI. USB, etc */
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#define BCM_BUS_PCIE_ROOT 1 /* bus 1, pcie root complex */
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#define BCM_BUS_PCIE_DEVICE 2 /* bus 2, pcie devices */
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/*
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* For integrated onchip WLAN support
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*/
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#define WLAN_ONCHIP_DEV_SLOT 0 /* predefined pci slot number to sit in */
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#define WLAN_ONCHIP_DEV_NUM 1 /* predefined instance of onchip wlan */
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#define WLAN_ONCHIP_PCI_ID 0x435f14e4
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#define WLAN_ONCHIP_RESOURCE_SIZE 0x2000
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#define WLAN_ONCHIP_PCI_HDR_DW_LEN 64
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#endif
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#if defined (__BCM_MAP_PART_H)
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/* chip specific is defined in PCIEH_MEMX_XXXX in bcm_map_part.h */
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#if defined(PCIEH)
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#ifdef PCIEH_MEM1_BASE
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#ifdef PCIEH_PCIE_IS_DEFAULT_TARGET
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/* for those are ubus default targets and can use a bigger MEM1 */
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#define BCM_PCIE_MEM1_BASE PCIEH_MEM1_BASE
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#define BCM_PCIE_MEM1_SIZE PCIEH_MEM1_SIZE
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#else
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#define BCM_PCIE_MEM1_BASE PCIEH_MEM2_BASE
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#define BCM_PCIE_MEM1_SIZE PCIEH_MEM2_SIZE
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#endif
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#else
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#error "PCIEH_MEM1_BASE/PCIEH_MEM1_SIZE not defined in xxxx_map_part.h"
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#endif
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#ifdef PCIEH_MEM2_BASE
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#ifdef PCIEH_PCIE_IS_DEFAULT_TARGET
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#define BCM_PCIE_MEM2_BASE PCIEH_MEM2_BASE
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#define BCM_PCIE_MEM2_SIZE PCIEH_MEM2_SIZE
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#else
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#define BCM_PCIE_MEM2_BASE PCIEH_MEM1_BASE
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#define BCM_PCIE_MEM2_SIZE PCIEH_MEM1_SIZE
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#endif
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#else
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#error "PCIEH_MEM2_BASE/PCIEH_MEM2_SIZE not defined in xxxx_map_part.h"
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#endif
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#endif /* PCIEH */
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/* PCI memory window in physical address space */
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/* Not a true PCI memory allocated by the chip
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assume PCIE MEM2 is not used,
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stealing unused PCIE MEM2 space to get PCI scanning going
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all devices hanging on pci bus 0 must fix-up their base address accordingly
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*/
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#if defined(MPI_BASE)
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#define BCM_PCI_MEM_BASE 0x11000000
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#define BCM_PCI_MEM_SIZE 0x01000000
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#else
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#define BCM_PCI_MEM_BASE BCM_PCIE_MEM2_BASE
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#define BCM_PCI_MEM_SIZE 0x00100000
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#endif
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/* Card bus memory window in physical address space */
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#define BCM_CB_MEM_BASE (BCM_PCI_MEM_BASE + BCM_PCI_MEM_SIZE)
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#define BCM_CB_MEM_SIZE 0x01000000
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/* IO window in physical address space */
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#define BCM_PCI_IO_BASE (BCM_CB_MEM_BASE + BCM_CB_MEM_SIZE)
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#define BCM_PCI_IO_SIZE 0x00010000
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#define BCM_PCI_ADDR_MASK 0x1fffffff
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/* PCI Configuration and I/O space acesss */
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#define BCM_PCI_CFG(d, f, o) ( (d << 11) | (f << 8) | (o/4 << 2) )
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/* fake USB PCI slot */
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#define USB_HOST_SLOT 9
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#define USB20_HOST_SLOT 10
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#define USB_BAR0_MEM_SIZE 0x0100
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#define BCM_HOST_MEM_SPACE1 0x10000000
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#define BCM_HOST_MEM_SPACE2 0x00000000
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/*
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* EBI bus clock is 33MHz and share with PCI bus
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* each clock cycle is 30ns.
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*/
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/* attribute memory access wait cnt for 4306 */
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#define PCMCIA_ATTR_CE_HOLD 3 // data hold time 70ns
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#define PCMCIA_ATTR_CE_SETUP 3 // data setup time 50ns
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#define PCMCIA_ATTR_INACTIVE 6 // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
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#define PCMCIA_ATTR_ACTIVE 10 // OE/WE pulse width 300ns
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/* common memory access wait cnt for 4306 */
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#define PCMCIA_MEM_CE_HOLD 1 // data hold time 30ns
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#define PCMCIA_MEM_CE_SETUP 1 // data setup time 30ns
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#define PCMCIA_MEM_INACTIVE 2 // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
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#define PCMCIA_MEM_ACTIVE 5 // OE/WE pulse width 150ns
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#define PCCARD_VCC_MASK 0x00070000 // Mask Reset also
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#define PCCARD_VCC_33V 0x00010000
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#define PCCARD_VCC_50V 0x00020000
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typedef enum {
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MPI_CARDTYPE_NONE, // No Card in slot
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MPI_CARDTYPE_PCMCIA, // 16-bit PCMCIA card in slot
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MPI_CARDTYPE_CARDBUS, // 32-bit CardBus card in slot
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} CardType;
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#define CARDBUS_SLOT 0 // Slot 0 is default for CardBus
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#define pcmciaAttrOffset 0x00200000
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#define pcmciaMemOffset 0x00000000
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// Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
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#define pcmciaIoOffset (BCM_PCI_IO_BASE + 0x80000)
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// Base Address is that mapped into the MPI ChipSelect registers.
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// UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
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#define pcmciaBase 0xbf000000
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#define pcmciaAttr (pcmciaAttrOffset | pcmciaBase)
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#define pcmciaMem (pcmciaMemOffset | pcmciaBase)
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#define pcmciaIo (pcmciaIoOffset | pcmciaBase)
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#endif
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