130 lines
5.1 KiB
C
130 lines
5.1 KiB
C
/*
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Copyright 2000-2010 Broadcom Corporation
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and to
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copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Notwithstanding the above, under no circumstances may you combine this
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software in any way with any other Broadcom software provided under a
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license other than the GPL, without Broadcom's express prior written
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consent.
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*/
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#ifndef __BCMSPIRES_H__
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#define __BCMSPIRES_H__
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#ifdef _CFE_
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struct spi_transfer {
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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unsigned int speed_hz;
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unsigned char prepend_cnt;
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unsigned char multi_bit_en;
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unsigned char multi_bit_start_offset;
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unsigned char hdr_len;
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unsigned char unit_size;
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unsigned char addr_len;
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unsigned char addr_offset;
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};
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#else
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#include <linux/spi/spi.h>
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#endif
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/* used to specify ctrlState for the interface BcmSpiReserveSlave2
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SPI_CONTROLLER_STATE_SET is used to differentiate a value of 0 which results in
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the controller using default values and the case where CPHA_EXT, GATE_CLK_SSOFF,
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CLK_POLARITY, and ASYNC_CLOCK all need to be 0
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SPI MODE sets the values for CPOL and CPHA
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SPI_CONTROLLER_STATE_CPHA_EXT will extend these modes
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CPOL = 0 -> base value of clock is 0
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CPHA = 0, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge
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CPHA = 1, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge
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CPHA = 0, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge
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CPHA = 1, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge
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CPOL = 1 -> base value of clock is 1
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CPHA = 0, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge
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CPHA = 1, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge
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CPHA = 0, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge
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CPHA = 1, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge
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*/
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#define SPI_CONTROLLER_STATE_SET (1 << 31)
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#define SPI_CONTROLLER_STATE_CPHA_EXT (1 << 30)
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#define SPI_CONTROLLER_STATE_GATE_CLK_SSOFF (1 << 29)
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#define SPI_CONTROLLER_STATE_ASYNC_CLOCK (1 << 28)
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#define SPI_CONTROLLER_STATE_MASK (0xf0000000)
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#ifndef SPI_CPHA
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#define SPI_CPHA 0x1
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#endif
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#ifndef SPI_CPOL
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#define SPI_CPOL 0x2
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#endif
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#ifndef SPI_MODE_0
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#define SPI_MODE_0 (0)
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#endif
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#ifndef SPI_MODE_1
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#define SPI_MODE_1 (SPI_CPHA)
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#endif
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#ifndef SPI_MODE_2
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#define SPI_MODE_2 (SPI_CPOL)
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#endif
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#ifndef SPI_MODE_3
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#endif
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#define SPI_CONTROLLER_MAX_SYNC_CLOCK 30000000
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/* set mode and controller state based on CHIP defaults
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these values do not apply to the legacy controller
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legacy controller uses SPI_MODE_3 and clock is not
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gated */
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#if defined(_BCM96816_) || defined(CONFIG_BCM96816)
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#define SPI_MODE_DEFAULT SPI_MODE_1
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#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF | SPI_CONTROLLER_STATE_CPHA_EXT)
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#else
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#define SPI_MODE_DEFAULT SPI_MODE_0
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#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF)
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#endif
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#ifndef _CFE_
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int BcmSpiReserveSlave(int busNum, int slaveId, int maxFreq);
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int BcmSpiReserveSlave2(int busNum, int slaveId, int maxFreq, int mode, int ctrlState);
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int BcmSpiReleaseSlave(int busNum, int slaveId);
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int BcmSpiSyncTrans(unsigned char *txBuf, unsigned char *rxBuf, int prependcnt, int nbytes, int busNum, int slaveId);
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int BcmSpiSyncMultTrans(struct spi_transfer *pSpiTransfer, int numTransfers, int busNum, int slaveId);
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#endif
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#define SPI_STATUS_OK (0)
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#define SPI_STATUS_INVALID_LEN (-1)
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#define SPI_STATUS_ERR (-2)
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/* legacy and HS controllers can coexist - use bus num to differentiate */
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#define LEG_SPI_BUS_NUM 0
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#define HS_SPI_BUS_NUM 1
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int BcmSpi_SetFlashCtrl( int opCode, int addrBytes, int dummyBytes, int busNum, int devId, int clockHz, int multibitEn );
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unsigned int BcmSpi_GetMaxRWSize( int busNum, int bAutoXfer);
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int BcmSpi_Read( unsigned char *msg_buf, int prependcnt, int nbytes, int busNum, int devId, int freqHz );
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int BcmSpi_Write( const unsigned char *msg_buf, int nbytes, int busNum, int devId, int freqHz );
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int BcmSpi_MultibitRead(struct spi_transfer * xfer, int busNum, int devId);
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int BcmSpi_SetCtrlState(int busNum, int slaveId, int spiMode, int ctrlState);
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#endif /* __BCMSPIRES_H__ */
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