157 lines
5.2 KiB
C
157 lines
5.2 KiB
C
/*
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<:label-BRCM:2012:DUAL/GPL:standard
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and
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to copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Not withstanding the above, under no circumstances may you combine
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this software in any way with any other Broadcom software provided
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under a license other than the GPL, without Broadcom's express prior
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written consent.
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:>
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*/
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#ifndef __BCM6318_CPU_H
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#define __BCM6318_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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#************************************************************************
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#* Coprocessor 0 Register Names
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#************************************************************************
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*/
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#define C0_BCM_CONFIG $22
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/*
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# Select 1
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# Bit 31: unused
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# Bits 30:25 MMU Size (Num TLB entries-1)
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# Bits 24:22 ICache sets/way (2^n * 64)
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# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
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# Bits 18:16 ICache Associativity (n+1) way
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# Bits 15:13 DCache sets/way (2^n * 64)
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# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
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# Bits 9:7 DCache Associativity (n+1) way
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# Bits 6:4 unused
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# Bit 3: 1=At least 1 watch register
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# Bit 2: 1=MIPS16 code compression implemented
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# Bit 1: 1=EJTAG implemented
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# Bit 0: 1=FPU implemented
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*/
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#define CP0_CFG_ISMSK (0x7 << 22)
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#define CP0_CFG_ISSHF 22
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#define CP0_CFG_ILMSK (0x7 << 19)
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#define CP0_CFG_ILSHF 19
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#define CP0_CFG_IAMSK (0x7 << 16)
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#define CP0_CFG_IASHF 16
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#define CP0_CFG_DSMSK (0x7 << 13)
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#define CP0_CFG_DSSHF 13
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#define CP0_CFG_DLMSK (0x7 << 10)
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#define CP0_CFG_DLSHF 10
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#define CP0_CFG_DAMSK (0x7 << 7)
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#define CP0_CFG_DASHF 7
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/*
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#************************************************************************
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#* Coprocessor 0 Broadcom Config Register Bits
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#************************************************************************
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*/
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#define CP0_BCM_CFG_ICSHEN (0x1 << 31)
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#define CP0_BCM_CFG_DCSHEN (0x1 << 30)
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#define CP0_BCM_CFG_TLBPD (0x1 << 28)
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#define CP0_BCM_CFG_CLF (0x1 << 20)
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#define CP0_BCM_CFG_BTHD (0x1 << 16) /* in select 5 */
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#if 0
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/*
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#************************************************************************
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#* Coprocessor 0 CMT Interrupt Register
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#************************************************************************
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*/
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#define CP0_CMT_XIR_4 (0x1 << 31)
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#define CP0_CMT_XIR_3 (0x1 << 30)
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#define CP0_CMT_XIR_2 (0x1 << 29)
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#define CP0_CMT_XIR_1 (0x1 << 28)
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#define CP0_CMT_XIR_0 (0x1 << 27)
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#define CP0_CMT_SIR_1 (0x1 << 16)
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#define CP0_CMT_SIR_0 (0x1 << 15)
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#define CP0_CMT_NMIR_TP1 (0x1 << 1)
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#define CP0_CMT_NMIR_TP0 (0x1 << 0)
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/*
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#************************************************************************
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#* Coprocessor 0 CMT Control Register
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#************************************************************************
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*/
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#define CP0_CMT_DSU_TP1 (0x1 << 30)
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#define CP0_CMT_TPS_SHFT 16
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#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT)
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#define CP0_CMT_PRIO_TP1 (0x1 << 5)
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#define CP0_CMT_PRIO_TP0 (0x1 << 4)
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#define CP0_CMT_RSTSE (0x1 << 0)
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/*
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#************************************************************************
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#* Coprocessor 0 CMT Local Register
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#************************************************************************
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*/
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#define CP0_CMT_TPID (0x1 << 31)
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#endif
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/*
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#************************************************************************
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#* MIPS Registers
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#************************************************************************
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*/
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/* The Core Register Space is specified in the Core Base Register(CP0 Reg 22, Sel 6) */
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#define MIPS_BASE_BOOT 0xbfa00000
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#define MIPS_BASE 0xff400000 /* CBR is relocated here in impl1_rom_boot.s */
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#define MIPS_RAC_CR0 0x00 // RAC Configuration Register
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#define RAC_FLH (1 << 8)
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#define RAC_DPF (1 << 6)
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#define RAC_NCH (1 << 5)
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#define RAC_C_INV (1 << 4)
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#define RAC_PF_D (1 << 3)
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#define RAC_PF_I (1 << 2)
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#define RAC_D (1 << 1)
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#define RAC_I (1 << 0)
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#define MIPS_RAC_ARR 0x04 // RAC Address Range Register
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#define RAC_UPB_SHFT 16
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#define RAC_LWB_SHFT 0
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#if 0
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#define MIPS_SBR 0x20 // System Base Register
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#define MIPS_TP0_ALT_BV 0x30000
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#define MIPS_TP1_ALT_BV 0x38000
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#define ENABLE_ALT_BV (1 << 19)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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