732 lines
22 KiB
C
732 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _X1_EMAC_H_
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#define _X1_EMAC_H_
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#include <linux/bitops.h>
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#include <linux/ptp_clock_kernel.h>
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#define PHY_INTF_RGMII BIT(2)
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/*
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* only valid for rmii mode
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* 0: ref clock from external phy
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* 1: ref clock from soc
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*/
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#define REF_CLK_SEL BIT(3)
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/*
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* emac function clock select
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* 0: 208M
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* 1: 312M
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*/
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#define FUNC_CLK_SEL BIT(4)
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/* only valid for rmii, invert tx clk */
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#define RMII_TX_CLK_SEL BIT(6)
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/* only valid for rmii, invert rx clk */
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#define RMII_RX_CLK_SEL BIT(7)
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/*
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* only valid for rgmiii
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* 0: tx clk from rx clk
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* 1: tx clk from soc
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*/
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#define RGMII_TX_CLK_SEL BIT(8)
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#define PHY_IRQ_EN BIT(12)
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#define AXI_SINGLE_ID BIT(13)
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#define RMII_TX_PHASE_OFFSET (16)
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#define RMII_TX_PHASE_MASK GENMASK(18, 16)
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#define RMII_RX_PHASE_OFFSET (20)
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#define RMII_RX_PHASE_MASK GENMASK(22, 20)
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#define RGMII_TX_PHASE_OFFSET (24)
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#define RGMII_TX_PHASE_MASK GENMASK(26, 24)
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#define RGMII_RX_PHASE_OFFSET (28)
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#define RGMII_RX_PHASE_MASK GENMASK(30, 28)
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#define EMAC_RX_DLINE_EN BIT(0)
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#define EMAC_RX_DLINE_STEP_OFFSET (4)
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#define EMAC_RX_DLINE_STEP_MASK GENMASK(5, 4)
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#define EMAC_RX_DLINE_CODE_OFFSET (8)
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#define EMAC_RX_DLINE_CODE_MASK GENMASK(15, 8)
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#define EMAC_TX_DLINE_EN BIT(16)
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#define EMAC_TX_DLINE_STEP_OFFSET (20)
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#define EMAC_TX_DLINE_STEP_MASK GENMASK(21, 20)
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#define EMAC_TX_DLINE_CODE_OFFSET (24)
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#define EMAC_TX_DLINE_CODE_MASK GENMASK(31, 24)
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/* DMA register set */
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#define DMA_CONFIGURATION 0x0000
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#define DMA_CONTROL 0x0004
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#define DMA_STATUS_IRQ 0x0008
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#define DMA_INTERRUPT_ENABLE 0x000C
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#define DMA_TRANSMIT_AUTO_POLL_COUNTER 0x0010
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#define DMA_TRANSMIT_POLL_DEMAND 0x0014
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#define DMA_RECEIVE_POLL_DEMAND 0x0018
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#define DMA_TRANSMIT_BASE_ADDRESS 0x001C
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#define DMA_RECEIVE_BASE_ADDRESS 0x0020
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#define DMA_MISSED_FRAME_COUNTER 0x0024
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#define DMA_STOP_FLUSH_COUNTER 0x0028
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#define DMA_RECEIVE_IRQ_MITIGATION_CTRL 0x002C
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#define DMA_CURRENT_TRANSMIT_DESCRIPTOR_POINTER 0x0030
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#define DMA_CURRENT_TRANSMIT_BUFFER_POINTER 0x0034
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#define DMA_CURRENT_RECEIVE_DESCRIPTOR_POINTER 0x0038
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#define DMA_CURRENT_RECEIVE_BUFFER_POINTER 0x003C
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/* MAC Register set */
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#define MAC_GLOBAL_CONTROL 0x0100
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#define MAC_TRANSMIT_CONTROL 0x0104
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#define MAC_RECEIVE_CONTROL 0x0108
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#define MAC_MAXIMUM_FRAME_SIZE 0x010C
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#define MAC_TRANSMIT_JABBER_SIZE 0x0110
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#define MAC_RECEIVE_JABBER_SIZE 0x0114
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#define MAC_ADDRESS_CONTROL 0x0118
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#define MAC_MDIO_CLK_DIV 0x011C
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#define MAC_ADDRESS1_HIGH 0x0120
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#define MAC_ADDRESS1_MED 0x0124
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#define MAC_ADDRESS1_LOW 0x0128
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#define MAC_ADDRESS2_HIGH 0x012C
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#define MAC_ADDRESS2_MED 0x0130
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#define MAC_ADDRESS2_LOW 0x0134
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#define MAC_ADDRESS3_HIGH 0x0138
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#define MAC_ADDRESS3_MED 0x013C
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#define MAC_ADDRESS3_LOW 0x0140
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#define MAC_ADDRESS4_HIGH 0x0144
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#define MAC_ADDRESS4_MED 0x0148
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#define MAC_ADDRESS4_LOW 0x014C
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#define MAC_MULTICAST_HASH_TABLE1 0x0150
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#define MAC_MULTICAST_HASH_TABLE2 0x0154
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#define MAC_MULTICAST_HASH_TABLE3 0x0158
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#define MAC_MULTICAST_HASH_TABLE4 0x015C
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#define MAC_FC_CONTROL 0x0160
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#define MAC_FC_PAUSE_FRAME_GENERATE 0x0164
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#define MAC_FC_SOURCE_ADDRESS_HIGH 0x0168
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#define MAC_FC_SOURCE_ADDRESS_MED 0x016C
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#define MAC_FC_SOURCE_ADDRESS_LOW 0x0170
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#define MAC_FC_DESTINATION_ADDRESS_HIGH 0x0174
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#define MAC_FC_DESTINATION_ADDRESS_MED 0x0178
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#define MAC_FC_DESTINATION_ADDRESS_LOW 0x017C
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#define MAC_FC_PAUSE_TIME_VALUE 0x0180
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#define MAC_MDIO_CONTROL 0x01A0
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#define MAC_MDIO_DATA 0x01A4
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#define MAC_RX_STATCTR_CONTROL 0x01A8
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#define MAC_RX_STATCTR_DATA_HIGH 0x01AC
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#define MAC_RX_STATCTR_DATA_LOW 0x01B0
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#define MAC_TX_STATCTR_CONTROL 0x01B4
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#define MAC_TX_STATCTR_DATA_HIGH 0x01B8
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#define MAC_TX_STATCTR_DATA_LOW 0x01BC
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#define MAC_TRANSMIT_FIFO_ALMOST_FULL 0x01C0
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#define MAC_TRANSMIT_PACKET_START_THRESHOLD 0x01C4
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#define MAC_RECEIVE_PACKET_START_THRESHOLD 0x01C8
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#define MAC_STATUS_IRQ 0x01E0
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#define MAC_INTERRUPT_ENABLE 0x01E4
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/* DMA_CONFIGURATION (0x0000) register bit info
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* 0-DMA controller in normal operation mode,
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* 1-DMA controller reset to default state,
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* clearing all internal state information
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*/
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#define MREGBIT_SOFTWARE_RESET BIT(0)
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#define MREGBIT_BURST_1WORD BIT(1)
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#define MREGBIT_BURST_2WORD BIT(2)
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#define MREGBIT_BURST_4WORD BIT(3)
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#define MREGBIT_BURST_8WORD BIT(4)
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#define MREGBIT_BURST_16WORD BIT(5)
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#define MREGBIT_BURST_32WORD BIT(6)
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#define MREGBIT_BURST_64WORD BIT(7)
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#define MREGBIT_BURST_LENGTH GENMASK(7, 1)
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#define MREGBIT_DESCRIPTOR_SKIP_LENGTH GENMASK(12, 8)
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/* For Receive and Transmit DMA operate in Big-Endian mode for Descriptors. */
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#define MREGBIT_DESCRIPTOR_BYTE_ORDERING BIT(13)
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#define MREGBIT_BIG_LITLE_ENDIAN BIT(14)
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#define MREGBIT_TX_RX_ARBITRATION BIT(15)
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#define MREGBIT_WAIT_FOR_DONE BIT(16)
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#define MREGBIT_STRICT_BURST BIT(17)
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#define MREGBIT_DMA_64BIT_MODE BIT(18)
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/* DMA_CONTROL (0x0004) register bit info */
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#define MREGBIT_START_STOP_TRANSMIT_DMA BIT(0)
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#define MREGBIT_START_STOP_RECEIVE_DMA BIT(1)
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/* DMA_STATUS_IRQ (0x0008) register bit info */
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#define MREGBIT_TRANSMIT_TRANSFER_DONE_IRQ BIT(0)
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#define MREGBIT_TRANSMIT_DES_UNAVAILABLE_IRQ BIT(1)
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#define MREGBIT_TRANSMIT_DMA_STOPPED_IRQ BIT(2)
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#define MREGBIT_RECEIVE_TRANSFER_DONE_IRQ BIT(4)
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#define MREGBIT_RECEIVE_DES_UNAVAILABLE_IRQ BIT(5)
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#define MREGBIT_RECEIVE_DMA_STOPPED_IRQ BIT(6)
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#define MREGBIT_RECEIVE_MISSED_FRAME_IRQ BIT(7)
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#define MREGBIT_MAC_IRQ BIT(8)
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#define MREGBIT_TRANSMIT_DMA_STATE GENMASK(18, 16)
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#define MREGBIT_RECEIVE_DMA_STATE GENMASK(23, 20)
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/* DMA_INTERRUPT_ENABLE ( 0x000C) register bit info */
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#define MREGBIT_TRANSMIT_TRANSFER_DONE_INTR_ENABLE BIT(0)
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#define MREGBIT_TRANSMIT_DES_UNAVAILABLE_INTR_ENABLE BIT(1)
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#define MREGBIT_TRANSMIT_DMA_STOPPED_INTR_ENABLE BIT(2)
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#define MREGBIT_RECEIVE_TRANSFER_DONE_INTR_ENABLE BIT(4)
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#define MREGBIT_RECEIVE_DES_UNAVAILABLE_INTR_ENABLE BIT(5)
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#define MREGBIT_RECEIVE_DMA_STOPPED_INTR_ENABLE BIT(6)
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#define MREGBIT_RECEIVE_MISSED_FRAME_INTR_ENABLE BIT(7)
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#define MREGBIT_MAC_INTR_ENABLE BIT(8)
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/* DMA RECEIVE IRQ MITIGATION CONTROL */
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#define MREGBIT_RECEIVE_IRQ_FRAME_COUNTER_MSK GENMASK(7, 0)
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#define MREGBIT_RECEIVE_IRQ_TIMEOUT_COUNTER_OFST (8)
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#define MREGBIT_RECEIVE_IRQ_TIMEOUT_COUNTER_MSK GENMASK(27, 8)
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#define MRGEBIT_RECEIVE_IRQ_FRAME_COUNTER_MODE BIT(30)
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#define MRGEBIT_RECEIVE_IRQ_MITIGATION_ENABLE BIT(31)
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/* MAC_GLOBAL_CONTROL (0x0100) register bit info */
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#define MREGBIT_SPEED GENMASK(1, 0)
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#define MREGBIT_SPEED_10M 0x0
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#define MREGBIT_SPEED_100M BIT(0)
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#define MREGBIT_SPEED_1000M BIT(1)
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#define MREGBIT_FULL_DUPLEX_MODE BIT(2)
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#define MREGBIT_RESET_RX_STAT_COUNTERS BIT(3)
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#define MREGBIT_RESET_TX_STAT_COUNTERS BIT(4)
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#define MREGBIT_UNICAST_WAKEUP_MODE BIT(8)
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#define MREGBIT_MAGIC_PACKET_WAKEUP_MODE BIT(9)
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/* MAC_TRANSMIT_CONTROL (0x0104) register bit info */
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#define MREGBIT_TRANSMIT_ENABLE BIT(0)
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#define MREGBIT_INVERT_FCS BIT(1)
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#define MREGBIT_DISABLE_FCS_INSERT BIT(2)
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#define MREGBIT_TRANSMIT_AUTO_RETRY BIT(3)
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#define MREGBIT_IFG_LEN GENMASK(6, 4)
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#define MREGBIT_PREAMBLE_LENGTH GENMASK(9, 7)
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/* MAC_RECEIVE_CONTROL (0x0108) register bit info */
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#define MREGBIT_RECEIVE_ENABLE BIT(0)
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#define MREGBIT_DISABLE_FCS_CHECK BIT(1)
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#define MREGBIT_STRIP_FCS BIT(2)
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#define MREGBIT_STORE_FORWARD BIT(3)
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#define MREGBIT_STATUS_FIRST BIT(4)
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#define MREGBIT_PASS_BAD_FRAMES BIT(5)
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#define MREGBIT_ACOOUNT_VLAN BIT(6)
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/* MAC_MAXIMUM_FRAME_SIZE (0x010C) register bit info */
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#define MREGBIT_MAX_FRAME_SIZE GENMASK(13, 0)
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/* MAC_TRANSMIT_JABBER_SIZE (0x0110) register bit info */
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#define MREGBIT_TRANSMIT_JABBER_SIZE GENMASK(15, 0)
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/* MAC_RECEIVE_JABBER_SIZE (0x0114) register bit info */
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#define MREGBIT_RECEIVE_JABBER_SIZE GENMASK(15, 0)
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/* MAC_ADDRESS_CONTROL (0x0118) register bit info */
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#define MREGBIT_MAC_ADDRESS1_ENABLE BIT(0)
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#define MREGBIT_MAC_ADDRESS2_ENABLE BIT(1)
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#define MREGBIT_MAC_ADDRESS3_ENABLE BIT(2)
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#define MREGBIT_MAC_ADDRESS4_ENABLE BIT(3)
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#define MREGBIT_INVERSE_MAC_ADDRESS1_ENABLE BIT(4)
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#define MREGBIT_INVERSE_MAC_ADDRESS2_ENABLE BIT(5)
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#define MREGBIT_INVERSE_MAC_ADDRESS3_ENABLE BIT(6)
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#define MREGBIT_INVERSE_MAC_ADDRESS4_ENABLE BIT(7)
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#define MREGBIT_PROMISCUOUS_MODE BIT(8)
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/* MAC_ADDRESSx_HIGH (0x0120) register bit info */
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#define MREGBIT_MAC_ADDRESS1_01_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS1_02_BYTE GENMASK(15, 8)
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/* MAC_ADDRESSx_MED (0x0124) register bit info */
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#define MREGBIT_MAC_ADDRESS1_03_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS1_04_BYTE GENMASK(15, 8)
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/* MAC_ADDRESSx_LOW (0x0128) register bit info */
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#define MREGBIT_MAC_ADDRESS1_05_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS1_06_BYTE GENMASK(15, 8)
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/* MAC_FC_CONTROL (0x0160) register bit info */
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#define MREGBIT_FC_DECODE_ENABLE BIT(0)
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#define MREGBIT_FC_GENERATION_ENABLE BIT(1)
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#define MREGBIT_AUTO_FC_GENERATION_ENABLE BIT(2)
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#define MREGBIT_MULTICAST_MODE BIT(3)
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#define MREGBIT_BLOCK_PAUSE_FRAMES BIT(4)
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/* MAC_FC_PAUSE_FRAME_GENERATE (0x0164) register bit info */
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#define MREGBIT_GENERATE_PAUSE_FRAME BIT(0)
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/* MAC_FC_SRC/DST_ADDRESS_HIGH (0x0168) register bit info */
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#define MREGBIT_MAC_ADDRESS_01_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS_02_BYTE GENMASK(15, 8)
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/* MAC_FC_SRC/DST_ADDRESS_MED (0x016C) register bit info */
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#define MREGBIT_MAC_ADDRESS_03_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS_04_BYTE GENMASK(15, 8)
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/* MAC_FC_SRC/DSTD_ADDRESS_LOW (0x0170) register bit info */
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#define MREGBIT_MAC_ADDRESS_05_BYTE GENMASK(7, 0)
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#define MREGBIT_MAC_ADDRESS_06_BYTE GENMASK(15, 8)
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/* MAC_FC_PAUSE_TIME_VALUE (0x0180) register bit info */
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#define MREGBIT_MAC_FC_PAUSE_TIME GENMASK(15, 0)
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/* MAC_MDIO_CONTROL (0x01A0) register bit info */
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#define MREGBIT_PHY_ADDRESS GENMASK(4, 0)
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#define MREGBIT_REGISTER_ADDRESS GENMASK(9, 5)
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#define MREGBIT_MDIO_READ_WRITE BIT(10)
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#define MREGBIT_START_MDIO_TRANS BIT(15)
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/* MAC_MDIO_DATA (0x01A4) register bit info */
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#define MREGBIT_MDIO_DATA GENMASK(15, 0)
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/* MAC_RX_STATCTR_CONTROL (0x01A8) register bit info */
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#define MREGBIT_RX_COUNTER_NUMBER GENMASK(4, 0)
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#define MREGBIT_START_RX_COUNTER_READ BIT(15)
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/* MAC_RX_STATCTR_DATA_HIGH (0x01AC) register bit info */
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#define MREGBIT_RX_STATCTR_DATA_HIGH GENMASK(15, 0)
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/* MAC_RX_STATCTR_DATA_LOW (0x01B0) register bit info */
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#define MREGBIT_RX_STATCTR_DATA_LOW GENMASK(15, 0)
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/* MAC_TX_STATCTR_CONTROL (0x01B4) register bit info */
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#define MREGBIT_TX_COUNTER_NUMBER GENMASK(4, 0)
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#define MREGBIT_START_TX_COUNTER_READ BIT(15)
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/* MAC_TX_STATCTR_DATA_HIGH (0x01B8) register bit info */
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#define MREGBIT_TX_STATCTR_DATA_HIGH GENMASK(15, 0)
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/* MAC_TX_STATCTR_DATA_LOW (0x01BC) register bit info */
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#define MREGBIT_TX_STATCTR_DATA_LOW GENMASK(15, 0)
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/* MAC_TRANSMIT_FIFO_ALMOST_FULL (0x01C0) register bit info */
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#define MREGBIT_TX_FIFO_AF GENMASK(13, 0)
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/* MAC_TRANSMIT_PACKET_START_THRESHOLD (0x01C4) register bit info */
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#define MREGBIT_TX_PACKET_START_THRESHOLD GENMASK(13, 0)
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/* MAC_RECEIVE_PACKET_START_THRESHOLD (0x01C8) register bit info */
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#define MREGBIT_RX_PACKET_START_THRESHOLD GENMASK(13, 0)
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/* MAC_STATUS_IRQ (0x01E0) register bit info */
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#define MREGBIT_MAC_UNDERRUN_IRQ BIT(0)
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#define MREGBIT_MAC_JABBER_IRQ BIT(1)
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/* MAC_INTERRUPT_ENABLE (0x01E4) register bit info */
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#define MREGBIT_MAC_UNDERRUN_INTERRUPT_ENABLE BIT(0)
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#define MREGBIT_JABBER_INTERRUPT_ENABLE BIT(1)
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/* Receive Descriptors */
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/* MAC_RECEIVE_DESCRIPTOR0 () register bit info */
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#define MREGBIT_FRAME_LENGTH GENMASK(13, 0)
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#define MREGBIT_APPLICATION_STATUS GENMASK(28, 14)
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#define MREGBIT_LAST_DESCRIPTOR BIT(29)
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#define MREGBIT_FIRST_DESCRIPTOR BIT(30)
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#define MREGBIT_OWN_BIT BIT(31)
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/* MAC_RECEIVE_DESCRIPTOR1 () register bit info */
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#define MREGBIT_BUFFER1_SIZE GENMASK(11, 0)
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#define MREGBIT_BUFFER2_SIZE GENMASK(23, 12)
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#define MREGBIT_SECOND_ADDRESS_CHAINED BIT(25)
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#define MREGBIT_END_OF_RING BIT(26)
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/* MAC_RECEIVE_DESCRIPTOR2 () register bit info */
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#define MREGBIT_BUFFER_ADDRESS1 GENMASK(31, 0)
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/* MAC_RECEIVE_DESCRIPTOR3 () register bit info */
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#define MREGBIT_BUFFER_ADDRESS1 GENMASK(31, 0)
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/* Transmit Descriptors */
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/* TD_TRANSMIT_DESCRIPTOR0 () register bit info */
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#define MREGBIT_TX_PACKET_STATUS GENMASK(29, 0)
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#define MREGBIT_OWN_BIT BIT(31)
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/* TD_TRANSMIT_DESCRIPTOR1 () register bit info */
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#define MREGBIT_BUFFER1_SIZE GENMASK(11, 0)
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#define MREGBIT_BUFFER2_SIZE GENMASK(23, 12)
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#define MREGBIT_FORCE_EOP_ERROR BIT(24)
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#define MREGBIT_SECOND_ADDRESS_CHAINED BIT(25)
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#define MREGBIT_END_OF_RING BIT(26)
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#define MREGBIT_DISABLE_PADDING BIT(27)
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#define MREGBIT_ADD_CRC_DISABLE BIT(28)
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#define MREGBIT_FIRST_SEGMENT BIT(29)
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#define MREGBIT_LAST_SEGMENT BIT(30)
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#define MREGBIT_INTERRUPT_ON_COMPLETION BIT(31)
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/* TD_TRANSMIT_DESCRIPTOR2 () register bit info */
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#define MREGBIT_BUFFER_ADDRESS1 GENMASK(31, 0)
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/* TD_TRANSMIT_DESCRIPTOR3 () register bit info */
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#define MREGBIT_BUFFER_ADDRESS1 GENMASK(31, 0)
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/* RX frame status */
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#define EMAC_RX_FRAME_ALIGN_ERR BIT(0)
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#define EMAC_RX_FRAME_RUNT BIT(1)
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#define EMAC_RX_FRAME_ETHERNET_TYPE BIT(2)
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#define EMAC_RX_FRAME_VLAN BIT(3)
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#define EMAC_RX_FRAME_MULTICAST BIT(4)
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#define EMAC_RX_FRAME_BROADCAST BIT(5)
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#define EMAC_RX_FRAME_CRC_ERR BIT(6)
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#define EMAC_RX_FRAME_MAX_LEN_ERR BIT(7)
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#define EMAC_RX_FRAME_JABBER_ERR BIT(8)
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#define EMAC_RX_FRAME_LENGTH_ERR BIT(9)
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#define EMAC_RX_FRAME_MAC_ADDR1_MATCH BIT(10)
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#define EMAC_RX_FRAME_MAC_ADDR2_MATCH BIT(11)
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#define EMAC_RX_FRAME_MAC_ADDR3_MATCH BIT(12)
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#define EMAC_RX_FRAME_MAC_ADDR4_MATCH BIT(13)
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#define EMAC_RX_FRAME_PAUSE_CTRL BIT(14)
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/* emac ptp 1588 register */
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#define PTP_1588_CTRL (0x300)
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#define TX_TIMESTAMP_EN BIT(1)
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#define RX_TIMESTAMP_EN BIT(2)
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#define RX_PTP_PKT_TYPE_OFST 3
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#define RX_PTP_PKT_TYPE_MSK GENMASK(5, 3)
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#define PTP_INRC_ATTR (0x304)
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#define INRC_VAL_MSK GENMASK(23, 0)
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#define INCR_PERIOD_OFST 24
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#define INCR_PERIOD_MSK GENMASK(31, 24)
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#define PTP_ETH_TYPE (0x308)
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#define PTP_ETH_TYPE_MSK GENMASK(15, 0)
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#define PTP_MSG_ID (0x30c)
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#define PTP_UDP_PORT (0x310)
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#define PTP_UDP_PORT_MSK GENMASK(15, 0)
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/* read current system time from controller */
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#define SYS_TIME_GET_LOW (0x320)
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#define SYS_TIME_GET_HI (0x324)
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#define SYS_TIME_ADJ_LOW (0x328)
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#define SYS_TIME_LOW_MSK GENMASK(31, 0)
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#define SYS_TIME_ADJ_HI (0x32c)
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#define SYS_TIME_IS_NEG BIT(31)
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#define TX_TIMESTAMP_LOW (0x330)
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#define TX_TIMESTAMP_HI (0x334)
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#define RX_TIMESTAMP_LOW (0x340)
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#define RX_TIMESTAMP_HI (0x344)
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#define RX_PTP_PKT_ATTR_LOW (0x348)
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#define PTP_SEQ_ID_MSK GENMASK(15, 0)
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#define PTP_SRC_ID_LOW_OFST 16
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#define PTP_SRC_ID_LOW_MSK GENMASK(31, 16)
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#define RX_PTP_PKT_ATTR_MID (0x34c)
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#define PTP_SRC_ID_MID_MSK GENMASK(31, 0)
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#define RX_PTP_PKT_ATTR_HI (0x350)
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#define PTP_SRC_ID_HI_MSK GENMASK(31, 0)
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#define PTP_1588_IRQ_STS (0x360)
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#define PTP_1588_IRQ_EN (0x364)
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#define PTP_TX_TIMESTAMP BIT(0)
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#define PTP_RX_TIMESTAMP BIT(1)
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/* emac ptp register */
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#define EMAC_DEFAULT_BUFSIZE 1536
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#define EMAC_RX_BUF_2K 2048
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#define EMAC_RX_BUF_4K 4096
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#define MAX_DATA_PWR_TX_DES 11
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#define MAX_DATA_LEN_TX_DES 2048 //2048=1<<11
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#define MAX_TX_STATS_NUM 12
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#define MAX_RX_STATS_NUM 25
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/* The sizes (in bytes) of a ethernet packet */
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#define ETHERNET_HEADER_SIZE 14
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#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 //With FCS
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#define MINIMUM_ETHERNET_FRAME_SIZE 64 //With FCS
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#define ETHERNET_FCS_SIZE 4
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#define MAXIMUM_ETHERNET_PACKET_SIZE \
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(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
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#define MINIMUM_ETHERNET_PACKET_SIZE \
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(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
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#define CRC_LENGTH ETHERNET_FCS_SIZE
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#define MAX_JUMBO_FRAME_SIZE 0x3F00
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#define TX_STORE_FORWARD_MODE 0x5EE
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#define EMAC_TX_FRAMES 64
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/* 40ms */
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#define EMAC_TX_COAL_TIMEOUT 40000
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#define EMAC_RX_FRAMES 64
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/* axi clk 312M, 1us = 312 cycle,
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* every packet almost take 120us when operate at 100Mbps
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* so we set 5 packet delay time which 600us as rx coal timeout
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*/
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#define EMAC_RX_COAL_TIMEOUT (36 * 312)
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/* only works for sizes that are powers of 2 */
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#define EMAC_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
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/* number of descriptors are required for len */
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#define EMAC_TXD_COUNT(S, X) (((S) >> (X)) + 1)
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/* calculate the number of descriptors unused */
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#define EMAC_DESC_UNUSED(R) \
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((((R)->nxt_clean > (R)->nxt_use) ? 0 : (R)->total_cnt) + \
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(R)->nxt_clean - (R)->nxt_use - 1)
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typedef struct ifreq st_ifreq, *pst_ifreq;
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enum rx_frame_status {
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frame_ok = 0,
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frame_discard,
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frame_max,
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};
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enum rx_ptp_type {
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PTP_V2_L2_ONLY = 0x0,
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PTP_V1_L4_ONLY = 0x1,
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PTP_V2_L2_L4 = 0x2,
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};
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enum ptp_event_msg_id {
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MSG_SYNC = 0x00,
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MSG_DELAY_REQ = 0x01,
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MSG_PDELAY_REQ = 0x02,
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MSG_PDELAY_RESP = 0x03,
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ALL_EVENTS = 0x03020100,
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};
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enum emac_state {
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EMAC_DOWN,
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EMAC_RESET_REQUESTED,
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EMAC_RESETING,
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EMAC_TASK_SCHED,
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EMAC_STATE_MAX,
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};
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/* Receive Descriptor structure */
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struct emac_rx_desc {
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u32 FramePacketLength:14;
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u32 ApplicationStatus:15;
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u32 LastDescriptor:1;
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u32 FirstDescriptor:1;
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u32 OWN:1;
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u32 BufferSize1:12;
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u32 BufferSize2:12;
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u32 Reserved1:1;
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u32 SecondAddressChained:1;
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u32 EndRing:1;
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u32 Reserved2:3;
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u32 rx_timestamp:1;
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u32 ptp_pkt:1;
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u32 BufferAddr1;
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u32 BufferAddr2;
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};
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/* Transmit Descriptor */
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struct emac_tx_desc {
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u32 FramePacketStatus:30;
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u32 tx_timestamp:1;
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u32 OWN:1;
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u32 BufferSize1:12;
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u32 BufferSize2:12;
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u32 ForceEOPError:1;
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u32 SecondAddressChained:1;
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u32 EndRing:1;
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u32 DisablePadding:1;
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u32 AddCRCDisable:1;
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u32 FirstSegment:1;
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|
u32 LastSegment:1;
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u32 InterruptOnCompletion:1;
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|
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u32 BufferAddr1;
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u32 BufferAddr2;
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|
};
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struct desc_buf {
|
|
u64 dma_addr;
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|
void *buff_addr;
|
|
u16 dma_len;
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|
u8 map_as_page;
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};
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/* Descriptor buffer structure */
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struct emac_tx_desc_buffer {
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|
struct sk_buff *skb;
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struct desc_buf buf[2];
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u8 timestamped;
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};
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/* Descriptor buffer structure */
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struct emac_desc_buffer {
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|
struct sk_buff *skb;
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|
u64 dma_addr;
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|
void *buff_addr;
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|
unsigned long ulTimeStamp;
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|
u16 dma_len;
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|
u8 map_as_page;
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|
u8 timestamped;
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|
};
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/* Descriptor ring structure */
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struct emac_desc_ring {
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|
/* virtual memory address to the descriptor ring memory */
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|
void *desc_addr;
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|
/* physical address of the descriptor ring */
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dma_addr_t desc_dma_addr;
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/* length of descriptor ring in bytes */
|
|
u32 total_size;
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|
/* number of descriptors in the ring */
|
|
u32 total_cnt;
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|
/* next descriptor to associate a buffer with */
|
|
u32 head;
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|
/* next descriptor to check for DD status bit */
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|
u32 tail;
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|
/* array of buffer information structs */
|
|
union {
|
|
struct emac_desc_buffer *desc_buf;
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|
struct emac_tx_desc_buffer *tx_desc_buf;
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|
};
|
|
};
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|
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struct emac_hw_stats {
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|
u32 tx_ok_pkts;
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|
u32 tx_total_pkts;
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|
u32 tx_ok_bytes;
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|
u32 tx_err_pkts;
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|
u32 tx_singleclsn_pkts;
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|
u32 tx_multiclsn_pkts;
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|
u32 tx_lateclsn_pkts;
|
|
u32 tx_excessclsn_pkts;
|
|
u32 tx_unicast_pkts;
|
|
u32 tx_multicast_pkts;
|
|
u32 tx_broadcast_pkts;
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|
u32 tx_pause_pkts;
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|
u32 rx_ok_pkts;
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|
u32 rx_total_pkts;
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|
u32 rx_crc_err_pkts;
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|
u32 rx_align_err_pkts;
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|
u32 rx_err_total_pkts;
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|
u32 rx_ok_bytes;
|
|
u32 rx_total_bytes;
|
|
u32 rx_unicast_pkts;
|
|
u32 rx_multicast_pkts;
|
|
u32 rx_broadcast_pkts;
|
|
u32 rx_pause_pkts;
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|
u32 rx_len_err_pkts;
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|
u32 rx_len_undersize_pkts;
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|
u32 rx_len_oversize_pkts;
|
|
u32 rx_len_fragment_pkts;
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|
u32 rx_len_jabber_pkts;
|
|
u32 rx_64_pkts;
|
|
u32 rx_65_127_pkts;
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|
u32 rx_128_255_pkts;
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|
u32 rx_256_511_pkts;
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|
u32 rx_512_1023_pkts;
|
|
u32 rx_1024_1518_pkts;
|
|
u32 rx_1519_plus_pkts;
|
|
u32 rx_drp_fifo_full_pkts;
|
|
u32 rx_truncate_fifo_full_pkts;
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|
|
|
spinlock_t stats_lock;
|
|
};
|
|
|
|
struct emac_priv;
|
|
struct emac_hw_ptp {
|
|
void (*config_hw_tstamping) (struct emac_priv *priv, u32 enable,
|
|
u8 rx_ptp_type, u32 ptp_msg_id);
|
|
u32 (*config_systime_increment)(struct emac_priv *priv, u32 ptp_clock,
|
|
u32 adj_clock);
|
|
int (*init_systime) (struct emac_priv *priv, u64 set_ns);
|
|
u64 (*get_phc_time)(struct emac_priv *priv);
|
|
u64 (*get_tx_timestamp)(struct emac_priv *priv);
|
|
u64 (*get_rx_timestamp)(struct emac_priv *priv);
|
|
};
|
|
|
|
struct emac_priv {
|
|
u32 dma_buf_sz;
|
|
u32 wol;
|
|
spinlock_t spStatsLock;
|
|
struct work_struct tx_timeout_task;
|
|
struct emac_desc_ring tx_ring;
|
|
struct emac_desc_ring rx_ring;
|
|
spinlock_t spTxLock;
|
|
struct net_device *ndev;
|
|
struct napi_struct napi;
|
|
struct platform_device *pdev;
|
|
struct clk *mac_clk;
|
|
struct clk *phy_clk;
|
|
struct clk *ptp_clk;
|
|
struct reset_control *reset;
|
|
void __iomem *iobase;
|
|
u32 apmu_base;
|
|
int irq;
|
|
int link;
|
|
int duplex;
|
|
int speed;
|
|
phy_interface_t phy_interface;
|
|
struct mii_bus *mii;
|
|
struct phy_device *phy;
|
|
struct emac_hw_stats *hw_stats;
|
|
u8 tx_clk_phase;
|
|
u8 rx_clk_phase;
|
|
u8 clk_tuning_way;
|
|
bool clk_tuning_enable;
|
|
unsigned long state;
|
|
u32 tx_threshold;
|
|
u32 rx_threshold;
|
|
u32 tx_ring_num;
|
|
u32 rx_ring_num;
|
|
u32 dma_burst_len;
|
|
u32 ref_clk_frm_soc;
|
|
void __iomem *ctrl_reg;
|
|
void __iomem *dline_reg;
|
|
s32 lpm_qos;
|
|
u32 tx_count_frames;
|
|
u32 tx_coal_frames;
|
|
u32 tx_coal_timeout;
|
|
struct timer_list txtimer;
|
|
struct ptp_clock *ptp_clock;
|
|
struct ptp_clock_info ptp_clock_ops;
|
|
spinlock_t ptp_lock;
|
|
int ptp_support;
|
|
u32 ptp_clk_rate;
|
|
int hwts_tx_en;
|
|
int hwts_rx_en;
|
|
struct emac_hw_ptp *hwptp;
|
|
struct delayed_work systim_overflow_work;
|
|
struct cyclecounter cc;
|
|
struct timecounter tc;
|
|
};
|
|
|
|
|
|
static inline void emac_wr(struct emac_priv *priv, u32 reg, u32 val)
|
|
{
|
|
writel(val, (priv->iobase + reg));
|
|
}
|
|
|
|
static inline int emac_rd(struct emac_priv *priv, u32 reg)
|
|
{
|
|
return readl(priv->iobase + reg);
|
|
}
|
|
|
|
int emac_init_hw(struct emac_priv *priv);
|
|
int emac_reset_hw(struct emac_priv *priv);
|
|
int emac_set_mac_addr(struct emac_priv *priv, const unsigned char *addr);
|
|
int emac_down(struct emac_priv *priv);
|
|
void emac_command_options(struct emac_priv *priv);
|
|
int emac_alloc_tx_resources(struct emac_priv *priv);
|
|
int emac_alloc_rx_resources(struct emac_priv *priv);
|
|
void emac_free_tx_resources(struct emac_priv *priv);
|
|
void emac_free_rx_resources(struct emac_priv *priv);
|
|
u32 ReadRxStatCounters(struct emac_priv *priv, u8 cnt);
|
|
u32 ReadTxStatCounters(struct emac_priv *priv, u8 cnt);
|
|
|
|
extern void emac_ptp_register(struct emac_priv *priv);
|
|
extern void emac_ptp_unregister(struct emac_priv *priv);
|
|
void emac_ptp_init(struct emac_priv *priv);
|
|
void emac_ptp_deinit(struct emac_priv *priv);
|
|
#endif /* _X1_EMAC_H_ */
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