408 lines
10 KiB
C
408 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Driver for Ky Mobile Storage Host Controller
|
|
*
|
|
* Copyright (C) 2023 Ky
|
|
*
|
|
* Author: Wilson Wan <long.wan@ky.com>
|
|
*/
|
|
|
|
#include <linux/acpi.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/dma-mapping.h>
|
|
#include <linux/iopoll.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/module.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_device.h>
|
|
#include <linux/reset.h>
|
|
#include <linux/sizes.h>
|
|
|
|
#include "sdhci-pltfm.h"
|
|
|
|
#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
|
|
|
|
/* DWCMSHC specific Mode Select value */
|
|
#define DWCMSHC_CTRL_HS400 0x7
|
|
|
|
/* DWC IP vendor area 1 pointer */
|
|
#define DWCMSHC_P_VENDOR_AREA1 0xe8
|
|
#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
|
|
/* Offset inside the vendor area 1 */
|
|
#define DWCMSHC_HOST_CTRL3 0x8
|
|
#define DWCMSHC_EMMC_CONTROL 0x2c
|
|
#define DWCMSHC_CARD_IS_EMMC BIT(0)
|
|
#define DWCMSHC_ENHANCED_STROBE BIT(8)
|
|
#define DWCMSHC_EMMC_ATCTRL 0x40
|
|
|
|
#define MAX_CLKS 1
|
|
|
|
#define BOUNDARY_OK(addr, len) \
|
|
((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
|
|
|
|
struct ky_priv {
|
|
/* Rockchip specified optional clocks */
|
|
struct clk_bulk_data clks[MAX_CLKS];
|
|
struct reset_control *reset;
|
|
u8 txclk_tapnum;
|
|
};
|
|
|
|
struct dwcmshc_priv {
|
|
struct clk *bus_clk;
|
|
int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
|
|
void *priv; /* pointer to SoC private stuff */
|
|
};
|
|
|
|
/*
|
|
* If DMA addr spans 128MB boundary, we split the DMA transfer into two
|
|
* so that each DMA transfer doesn't exceed the boundary.
|
|
*/
|
|
static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
|
|
dma_addr_t addr, int len, unsigned int cmd)
|
|
{
|
|
int tmplen, offset;
|
|
|
|
if (likely(!len || BOUNDARY_OK(addr, len))) {
|
|
sdhci_adma_write_desc(host, desc, addr, len, cmd);
|
|
return;
|
|
}
|
|
|
|
offset = addr & (SZ_128M - 1);
|
|
tmplen = SZ_128M - offset;
|
|
sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
|
|
|
|
addr += tmplen;
|
|
len -= tmplen;
|
|
sdhci_adma_write_desc(host, desc, addr, len, cmd);
|
|
}
|
|
|
|
static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
|
|
if (pltfm_host->clk)
|
|
return sdhci_pltfm_clk_get_max_clock(host);
|
|
else
|
|
return pltfm_host->clock;
|
|
}
|
|
|
|
static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
|
|
struct mmc_request *mrq)
|
|
{
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
|
|
/*
|
|
* No matter V4 is enabled or not, ARGUMENT2 register is 32-bit
|
|
* block count register which doesn't support stuff bits of
|
|
* CMD23 argument on dwcmsch host controller.
|
|
*/
|
|
if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))
|
|
host->flags &= ~SDHCI_AUTO_CMD23;
|
|
else
|
|
host->flags |= SDHCI_AUTO_CMD23;
|
|
}
|
|
|
|
static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
{
|
|
dwcmshc_check_auto_cmd23(mmc, mrq);
|
|
|
|
sdhci_request(mmc, mrq);
|
|
}
|
|
|
|
static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
|
|
unsigned int timing)
|
|
{
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
u16 ctrl, ctrl_2;
|
|
|
|
ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
|
|
/* Select Bus Speed Mode for host */
|
|
ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
|
|
if ((timing == MMC_TIMING_MMC_HS200) ||
|
|
(timing == MMC_TIMING_UHS_SDR104))
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
|
|
else if (timing == MMC_TIMING_UHS_SDR12)
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
|
|
else if ((timing == MMC_TIMING_UHS_SDR25) ||
|
|
(timing == MMC_TIMING_MMC_HS))
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
|
|
else if (timing == MMC_TIMING_UHS_SDR50)
|
|
ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
|
|
else if ((timing == MMC_TIMING_UHS_DDR50) ||
|
|
(timing == MMC_TIMING_MMC_DDR52))
|
|
ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
|
|
else if (timing == MMC_TIMING_MMC_HS400) {
|
|
/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
|
|
ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
|
|
ctrl |= DWCMSHC_CARD_IS_EMMC;
|
|
sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
|
|
|
|
ctrl_2 |= DWCMSHC_CTRL_HS400;
|
|
}
|
|
|
|
sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
|
|
}
|
|
|
|
static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,
|
|
struct mmc_ios *ios)
|
|
{
|
|
u32 vendor;
|
|
struct sdhci_host *host = mmc_priv(mmc);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
|
|
|
|
vendor = sdhci_readl(host, reg);
|
|
if (ios->enhanced_strobe)
|
|
vendor |= DWCMSHC_ENHANCED_STROBE;
|
|
else
|
|
vendor &= ~DWCMSHC_ENHANCED_STROBE;
|
|
|
|
sdhci_writel(host, vendor, reg);
|
|
}
|
|
|
|
static const struct sdhci_ops sdhci_dwcmshc_ops = {
|
|
.set_clock = sdhci_set_clock,
|
|
.set_bus_width = sdhci_set_bus_width,
|
|
.set_uhs_signaling = dwcmshc_set_uhs_signaling,
|
|
.get_max_clock = dwcmshc_get_max_clock,
|
|
.reset = sdhci_reset,
|
|
.adma_write_desc = dwcmshc_adma_write_desc,
|
|
};
|
|
|
|
static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
|
|
.ops = &sdhci_dwcmshc_ops,
|
|
.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
|
|
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
|
|
};
|
|
|
|
static int dwcmshc_ky_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
|
|
{
|
|
int err;
|
|
struct ky_priv *priv = dwc_priv->priv;
|
|
|
|
priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
|
|
if (IS_ERR(priv->reset)) {
|
|
err = PTR_ERR(priv->reset);
|
|
dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
|
|
return err;
|
|
}
|
|
reset_control_assert(priv->reset);
|
|
udelay(1);
|
|
reset_control_deassert(priv->reset);
|
|
|
|
priv->clks[0].id = "axi";
|
|
err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), MAX_CLKS,
|
|
priv->clks);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = clk_bulk_prepare_enable(MAX_CLKS, priv->clks);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
|
|
{
|
|
.compatible = "ky,x1-pro-sdhci",
|
|
.data = &sdhci_dwcmshc_pdata,
|
|
},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
|
|
|
|
static int dwcmshc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_host *host;
|
|
struct dwcmshc_priv *priv;
|
|
struct ky_priv *sm_priv = NULL;
|
|
const struct sdhci_pltfm_data *pltfm_data;
|
|
int err;
|
|
u32 extra;
|
|
|
|
pltfm_data = device_get_match_data(&pdev->dev);
|
|
if (!pltfm_data) {
|
|
dev_err(&pdev->dev, "Error: No device match data found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
host = sdhci_pltfm_init(pdev, pltfm_data,
|
|
sizeof(struct dwcmshc_priv));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
/*
|
|
* extra adma table cnt for cross 128M boundary handling.
|
|
*/
|
|
extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
|
|
if (extra > SDHCI_MAX_SEGS)
|
|
extra = SDHCI_MAX_SEGS;
|
|
host->adma_table_cnt += extra;
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
priv = sdhci_pltfm_priv(pltfm_host);
|
|
|
|
if (dev->of_node) {
|
|
pltfm_host->clk = devm_clk_get(dev, "core");
|
|
if (IS_ERR(pltfm_host->clk)) {
|
|
err = PTR_ERR(pltfm_host->clk);
|
|
dev_err(dev, "failed to get core clk: %d\n", err);
|
|
goto free_pltfm;
|
|
}
|
|
err = clk_prepare_enable(pltfm_host->clk);
|
|
if (err)
|
|
goto free_pltfm;
|
|
|
|
priv->bus_clk = devm_clk_get(dev, "bus");
|
|
if (!IS_ERR(priv->bus_clk))
|
|
clk_prepare_enable(priv->bus_clk);
|
|
}
|
|
|
|
err = mmc_of_parse(host->mmc);
|
|
if (err)
|
|
goto free_pltfm;
|
|
|
|
sdhci_get_of_property(pdev);
|
|
|
|
priv->vendor_specific_area1 =
|
|
sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
|
|
|
|
host->mmc_host_ops.request = dwcmshc_request;
|
|
host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
|
|
|
|
sm_priv = devm_kzalloc(&pdev->dev, sizeof(struct ky_priv), GFP_KERNEL);
|
|
if (!sm_priv) {
|
|
err = -ENOMEM;
|
|
goto free_pltfm;
|
|
}
|
|
|
|
priv->priv = sm_priv;
|
|
|
|
err = dwcmshc_ky_init(host, priv);
|
|
if (err)
|
|
goto free_pltfm;
|
|
host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
|
|
|
|
sdhci_enable_v4_mode(host);
|
|
|
|
err = sdhci_setup_host(host);
|
|
if (err)
|
|
goto err_clk;
|
|
|
|
err = __sdhci_add_host(host);
|
|
if (err)
|
|
goto err_setup_host;
|
|
|
|
return 0;
|
|
|
|
err_setup_host:
|
|
sdhci_cleanup_host(host);
|
|
err_clk:
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
if (sm_priv)
|
|
clk_bulk_disable_unprepare(MAX_CLKS,
|
|
sm_priv->clks);
|
|
free_pltfm:
|
|
sdhci_pltfm_free(pdev);
|
|
return err;
|
|
}
|
|
|
|
static int dwcmshc_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct ky_priv *sm_priv = priv->priv;
|
|
|
|
sdhci_remove_host(host, 0);
|
|
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
if (sm_priv)
|
|
clk_bulk_disable_unprepare(MAX_CLKS, sm_priv->clks);
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwcmshc_suspend(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct ky_priv *sm_priv = priv->priv;
|
|
int ret;
|
|
|
|
ret = sdhci_suspend_host(host);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
if (!IS_ERR(priv->bus_clk))
|
|
clk_disable_unprepare(priv->bus_clk);
|
|
|
|
if (sm_priv)
|
|
clk_bulk_disable_unprepare(MAX_CLKS,
|
|
sm_priv->clks);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dwcmshc_resume(struct device *dev)
|
|
{
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
|
struct ky_priv *sm_priv = priv->priv;
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(pltfm_host->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!IS_ERR(priv->bus_clk)) {
|
|
ret = clk_prepare_enable(priv->bus_clk);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (sm_priv) {
|
|
ret = clk_bulk_prepare_enable(MAX_CLKS, sm_priv->clks);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return sdhci_resume_host(host);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
|
|
|
|
static struct platform_driver sdhci_dwcmshc_driver = {
|
|
.driver = {
|
|
.name = "sdhci-dwcmshc",
|
|
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
|
.of_match_table = sdhci_dwcmshc_dt_ids,
|
|
.acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
|
|
.pm = &dwcmshc_pmops,
|
|
},
|
|
.probe = dwcmshc_probe,
|
|
.remove = dwcmshc_remove,
|
|
};
|
|
module_platform_driver(sdhci_dwcmshc_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI platform driver for Ky");
|
|
MODULE_AUTHOR("Wilson Wan <long.wan@ky.com>");
|
|
MODULE_LICENSE("GPL v2");
|