077e5f4f55
D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based on a single die, or at a pair of dies derived from the same design. D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP variants. Because the original design supported both ARM and RISC-V CPUs, some peripherals are duplicated. In addition, all variants except D1s contain a HiFi 4 DSP with its own set of peripherals. The devicetrees are organized to minimize duplication: - Common perhiperals are described in sunxi-d1s-t113.dtsi - DSP-related peripherals are described in sunxi-d1-t113.dtsi - RISC-V specific hardware is described in sun20i-d1s.dtsi - Functionality unique to the D1 variant is described in sun20i-d1.dtsi The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230126045738.47903-5-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
16 lines
394 B
Plaintext
16 lines
394 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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/ {
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soc {
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dsp_wdt: watchdog@1700400 {
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compatible = "allwinner,sun20i-d1-wdt";
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reg = <0x1700400 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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status = "reserved";
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};
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};
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};
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