74641f4a79
Add pwm node to support fan on exynosautov9-sadk board. PWM channel 3 of ExynosAutov9 is connected to fan for SoC cooling in SADK board. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20230718062200.79306-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
89 lines
1.5 KiB
Plaintext
89 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung ExynosAutov9 SADK board device tree source
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "exynosautov9.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Samsung ExynosAuto v9 SADK board";
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compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &serial_0;
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};
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chosen {
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stdout-path = &serial_0;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x77000000>,
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<0x8 0x80000000 0x1 0x7ba00000>,
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<0xa 0x00000000 0x2 0x00000000>;
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};
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ufs_0_fixed_vcc_reg: regulator-0 {
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compatible = "regulator-fixed";
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regulator-name = "ufs-vcc";
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gpio = <&gpq0 1 GPIO_ACTIVE_HIGH>;
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regulator-boot-on;
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enable-active-high;
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};
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ufs_1_fixed_vcc_reg: regulator-1 {
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compatible = "regulator-fixed";
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regulator-name = "ufs-vcc";
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gpio = <&gpg2 2 GPIO_ACTIVE_HIGH>;
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regulator-boot-on;
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enable-active-high;
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_tout3>;
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status = "okay";
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};
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&serial_0 {
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pinctrl-0 = <&uart0_bus_dual>;
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status = "okay";
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};
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&ufs_0_phy {
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status = "okay";
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};
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&ufs_1_phy {
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status = "okay";
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};
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&ufs_0 {
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status = "okay";
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vcc-supply = <&ufs_0_fixed_vcc_reg>;
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};
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&ufs_1 {
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status = "okay";
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vcc-supply = <&ufs_1_fixed_vcc_reg>;
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};
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&usi_0 {
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samsung,clkreq-on; /* needed for UART mode */
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status = "okay";
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};
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&xtcxo {
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clock-frequency = <26000000>;
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};
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