238 lines
6.6 KiB
Diff
238 lines
6.6 KiB
Diff
From 2f5df30a7b913069c8fce22dc702e0d7c76ef361 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 20 Jan 2016 12:09:14 +0100
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Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
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Add the registers, callbacks and data structures required to make the
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wrapper work on MT2701 and MT7623.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/soc/mediatek/mtk-pmic-wrap.c | 154 ++++++++++++++++++++++++++++++++++
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1 file changed, 154 insertions(+)
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diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
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index 0e4ebb8..3c3e56d 100644
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--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
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+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
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@@ -52,6 +52,7 @@
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#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
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/* macro for manual command */
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+#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
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#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
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#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
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#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
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@@ -200,6 +201,13 @@ enum pwrap_regs {
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PWRAP_DCM_EN,
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PWRAP_DCM_DBC_PRD,
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+ /* MT2701 only regs */
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+ PWRAP_ADC_CMD_ADDR,
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+ PWRAP_PWRAP_ADC_CMD,
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+ PWRAP_ADC_RDY_ADDR,
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+ PWRAP_ADC_RDATA_ADDR1,
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+ PWRAP_ADC_RDATA_ADDR2,
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+
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/* MT8135 only regs */
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PWRAP_CSHEXT,
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PWRAP_EVENT_IN_EN,
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@@ -236,6 +244,92 @@ enum pwrap_regs {
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PWRAP_CIPHER_EN,
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};
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+static int mt2701_regs[] = {
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+ [PWRAP_MUX_SEL] = 0x0,
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+ [PWRAP_WRAP_EN] = 0x4,
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+ [PWRAP_DIO_EN] = 0x8,
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+ [PWRAP_SIDLY] = 0xc,
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+ [PWRAP_RDDMY] = 0x18,
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+ [PWRAP_SI_CK_CON] = 0x1c,
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+ [PWRAP_CSHEXT_WRITE] = 0x20,
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+ [PWRAP_CSHEXT_READ] = 0x24,
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+ [PWRAP_CSLEXT_START] = 0x28,
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+ [PWRAP_CSLEXT_END] = 0x2c,
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+ [PWRAP_STAUPD_PRD] = 0x30,
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+ [PWRAP_STAUPD_GRPEN] = 0x34,
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+ [PWRAP_STAUPD_MAN_TRIG] = 0x38,
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+ [PWRAP_STAUPD_STA] = 0x3c,
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+ [PWRAP_WRAP_STA] = 0x44,
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+ [PWRAP_HARB_INIT] = 0x48,
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+ [PWRAP_HARB_HPRIO] = 0x4c,
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+ [PWRAP_HIPRIO_ARB_EN] = 0x50,
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+ [PWRAP_HARB_STA0] = 0x54,
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+ [PWRAP_HARB_STA1] = 0x58,
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+ [PWRAP_MAN_EN] = 0x5c,
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+ [PWRAP_MAN_CMD] = 0x60,
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+ [PWRAP_MAN_RDATA] = 0x64,
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+ [PWRAP_MAN_VLDCLR] = 0x68,
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+ [PWRAP_WACS0_EN] = 0x6c,
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+ [PWRAP_INIT_DONE0] = 0x70,
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+ [PWRAP_WACS0_CMD] = 0x74,
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+ [PWRAP_WACS0_RDATA] = 0x78,
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+ [PWRAP_WACS0_VLDCLR] = 0x7c,
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+ [PWRAP_WACS1_EN] = 0x80,
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+ [PWRAP_INIT_DONE1] = 0x84,
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+ [PWRAP_WACS1_CMD] = 0x88,
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+ [PWRAP_WACS1_RDATA] = 0x8c,
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+ [PWRAP_WACS1_VLDCLR] = 0x90,
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+ [PWRAP_WACS2_EN] = 0x94,
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+ [PWRAP_INIT_DONE2] = 0x98,
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+ [PWRAP_WACS2_CMD] = 0x9c,
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+ [PWRAP_WACS2_RDATA] = 0xa0,
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+ [PWRAP_WACS2_VLDCLR] = 0xa4,
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+ [PWRAP_INT_EN] = 0xa8,
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+ [PWRAP_INT_FLG_RAW] = 0xac,
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+ [PWRAP_INT_FLG] = 0xb0,
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+ [PWRAP_INT_CLR] = 0xb4,
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+ [PWRAP_SIG_ADR] = 0xb8,
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+ [PWRAP_SIG_MODE] = 0xbc,
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+ [PWRAP_SIG_VALUE] = 0xc0,
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+ [PWRAP_SIG_ERRVAL] = 0xc4,
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+ [PWRAP_CRC_EN] = 0xc8,
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+ [PWRAP_TIMER_EN] = 0xcc,
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+ [PWRAP_TIMER_STA] = 0xd0,
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+ [PWRAP_WDT_UNIT] = 0xd4,
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+ [PWRAP_WDT_SRC_EN] = 0xd8,
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+ [PWRAP_WDT_FLG] = 0xdc,
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+ [PWRAP_DEBUG_INT_SEL] = 0xe0,
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+ [PWRAP_DVFS_ADR0] = 0xe4,
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+ [PWRAP_DVFS_WDATA0] = 0xe8,
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+ [PWRAP_DVFS_ADR1] = 0xec,
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+ [PWRAP_DVFS_WDATA1] = 0xf0,
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+ [PWRAP_DVFS_ADR2] = 0xf4,
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+ [PWRAP_DVFS_WDATA2] = 0xf8,
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+ [PWRAP_DVFS_ADR3] = 0xfc,
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+ [PWRAP_DVFS_WDATA3] = 0x100,
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+ [PWRAP_DVFS_ADR4] = 0x104,
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+ [PWRAP_DVFS_WDATA4] = 0x108,
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+ [PWRAP_DVFS_ADR5] = 0x10c,
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+ [PWRAP_DVFS_WDATA5] = 0x110,
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+ [PWRAP_DVFS_ADR6] = 0x114,
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+ [PWRAP_DVFS_WDATA6] = 0x118,
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+ [PWRAP_DVFS_ADR7] = 0x11c,
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+ [PWRAP_DVFS_WDATA7] = 0x120,
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+ [PWRAP_CIPHER_KEY_SEL] = 0x124,
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+ [PWRAP_CIPHER_IV_SEL] = 0x128,
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+ [PWRAP_CIPHER_EN] = 0x12c,
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+ [PWRAP_CIPHER_RDY] = 0x130,
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+ [PWRAP_CIPHER_MODE] = 0x134,
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+ [PWRAP_CIPHER_SWRST] = 0x138,
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+ [PWRAP_DCM_EN] = 0x13c,
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+ [PWRAP_DCM_DBC_PRD] = 0x140,
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+ [PWRAP_ADC_CMD_ADDR] = 0x144,
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+ [PWRAP_PWRAP_ADC_CMD] = 0x148,
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+ [PWRAP_ADC_RDY_ADDR] = 0x14c,
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+ [PWRAP_ADC_RDATA_ADDR1] = 0x150,
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+ [PWRAP_ADC_RDATA_ADDR2] = 0x154,
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+};
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+
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static int mt8173_regs[] = {
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[PWRAP_MUX_SEL] = 0x0,
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[PWRAP_WRAP_EN] = 0x4,
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@@ -397,6 +491,7 @@ enum pmic_type {
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};
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enum pwrap_type {
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+ PWRAP_MT2701,
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PWRAP_MT8135,
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PWRAP_MT8173,
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};
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@@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
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return 0;
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}
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+static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
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+{
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+ switch (wrp->slave->type) {
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+ case PMIC_MT6397:
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+ pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
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+ pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
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+ pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
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+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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+ break;
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+
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+ case PMIC_MT6323:
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+ pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
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+ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
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+ 0x8);
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+ pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
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+ pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
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+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
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+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
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{
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return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
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@@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
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pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
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pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
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break;
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+ case PWRAP_MT2701:
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case PWRAP_MT8173:
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pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
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break;
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@@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
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return 0;
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}
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+static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
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+{
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+ /* GPS_INTF initialization */
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+ switch (wrp->slave->type) {
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+ case PMIC_MT6323:
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+ pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
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+ pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
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+ pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
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+ pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
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+ pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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static int pwrap_init(struct pmic_wrapper *wrp)
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{
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int ret;
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@@ -916,6 +1055,18 @@ static const struct of_device_id of_slave_match_tbl[] = {
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};
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MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
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+static const struct pmic_wrapper_type pwrap_mt2701 = {
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+ .regs = mt2701_regs,
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+ .type = PWRAP_MT2701,
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+ .arb_en_all = 0x3f,
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+ .int_en_all = ~(BIT(31) | BIT(2)),
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+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
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+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
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+ .has_bridge = 0,
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+ .init_reg_clock = pwrap_mt2701_init_reg_clock,
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+ .init_soc_specific = pwrap_mt2701_init_soc_specific,
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+};
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+
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static struct pmic_wrapper_type pwrap_mt8135 = {
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.regs = mt8135_regs,
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.type = PWRAP_MT8135,
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@@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
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static struct of_device_id of_pwrap_match_tbl[] = {
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{
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+ .compatible = "mediatek,mt2701-pwrap",
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+ .data = &pwrap_mt2701,
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+ }, {
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.compatible = "mediatek,mt8135-pwrap",
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.data = &pwrap_mt8135,
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}, {
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--
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1.7.10.4
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