103 lines
3.0 KiB
Diff
103 lines
3.0 KiB
Diff
--- a/arch/mips/ath79/irq.c
|
|
+++ b/arch/mips/ath79/irq.c
|
|
@@ -26,6 +26,9 @@
|
|
#include "common.h"
|
|
#include "machtypes.h"
|
|
|
|
+static struct irq_chip ip2_chip;
|
|
+static struct irq_chip ip3_chip;
|
|
+
|
|
static void ath79_misc_irq_handler(struct irq_desc *desc)
|
|
{
|
|
void __iomem *base = ath79_reset_base;
|
|
@@ -145,8 +148,7 @@ static void ar934x_ip2_irq_init(void)
|
|
|
|
for (i = ATH79_IP2_IRQ_BASE;
|
|
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip,
|
|
- handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
|
|
}
|
|
@@ -174,7 +176,7 @@ static void qca953x_irq_init(void)
|
|
|
|
for (i = ATH79_IP2_IRQ_BASE;
|
|
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
|
|
}
|
|
@@ -238,15 +240,13 @@ static void qca955x_irq_init(void)
|
|
|
|
for (i = ATH79_IP2_IRQ_BASE;
|
|
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip,
|
|
- handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
|
|
|
|
for (i = ATH79_IP3_IRQ_BASE;
|
|
i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip,
|
|
- handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
|
|
}
|
|
@@ -331,13 +331,13 @@ static void qca956x_irq_init(void)
|
|
|
|
for (i = ATH79_IP2_IRQ_BASE;
|
|
i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
|
|
|
|
for (i = ATH79_IP3_IRQ_BASE;
|
|
i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
|
|
- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
|
+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
|
|
|
|
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
|
|
|
|
@@ -463,8 +463,36 @@ IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar71
|
|
|
|
#endif
|
|
|
|
+static void ath79_ip2_disable(struct irq_data *data)
|
|
+{
|
|
+ disable_irq(ATH79_CPU_IRQ(2));
|
|
+}
|
|
+
|
|
+static void ath79_ip2_enable(struct irq_data *data)
|
|
+{
|
|
+ enable_irq(ATH79_CPU_IRQ(2));
|
|
+}
|
|
+
|
|
+static void ath79_ip3_disable(struct irq_data *data)
|
|
+{
|
|
+ disable_irq(ATH79_CPU_IRQ(3));
|
|
+}
|
|
+
|
|
+static void ath79_ip3_enable(struct irq_data *data)
|
|
+{
|
|
+ enable_irq(ATH79_CPU_IRQ(3));
|
|
+}
|
|
+
|
|
void __init arch_init_irq(void)
|
|
{
|
|
+ ip2_chip = dummy_irq_chip;
|
|
+ ip2_chip.irq_disable = ath79_ip2_disable;
|
|
+ ip2_chip.irq_enable = ath79_ip2_enable;
|
|
+
|
|
+ ip3_chip = dummy_irq_chip;
|
|
+ ip3_chip.irq_disable = ath79_ip3_disable;
|
|
+ ip3_chip.irq_enable = ath79_ip3_enable;
|
|
+
|
|
if (mips_machtype == ATH79_MACH_GENERIC_OF) {
|
|
irqchip_init();
|
|
return;
|