283d7789ee
A few trivial changes were needed to adapt to upstream framework changes. Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43499
375 lines
8.5 KiB
C
375 lines
8.5 KiB
C
#include <common.h>
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#include <spl.h>
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#include <phy.h>
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#include <netdev.h>
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#include <ide.h>
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#include <nand.h>
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#include <asm/arch/spl.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sysctl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SPL_BUILD
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#ifdef DEBUG
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#define DILIGENCE (1048576/4)
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static int test_memory(u32 memory)
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{
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volatile u32 *read;
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volatile u32 *write;
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const u32 INIT_PATTERN = 0xAA55AA55;
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const u32 INC_PATTERN = 0x01030507;
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u32 pattern;
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int check;
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int i;
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check = 0;
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read = write = (volatile u32 *) memory;
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pattern = INIT_PATTERN;
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for (i = 0; i < DILIGENCE; i++) {
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*write++ = pattern;
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pattern += INC_PATTERN;
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}
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puts("testing\n");
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pattern = INIT_PATTERN;
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for (i = 0; i < DILIGENCE; i++) {
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check += (pattern == *read++) ? 1 : 0;
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pattern += INC_PATTERN;
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}
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return (check == DILIGENCE) ? 0 : -1;
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}
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#endif
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void uart_init(void)
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{
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/* Reset UART1 */
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reset_block(SYS_CTRL_RST_UART1, 1);
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udelay(100);
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reset_block(SYS_CTRL_RST_UART1, 0);
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udelay(100);
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/* Setup pin mux'ing for UART1 */
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pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
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pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
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}
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extern void init_ddr(int mhz);
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void board_inithw(void)
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{
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int plla_freq;
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#ifdef DEBUG
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int i;
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#endif /* DEBUG */
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timer_init();
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uart_init();
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preloader_console_init();
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plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
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init_ddr(plla_freq);
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#ifdef DEBUG
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if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
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puts("memory test failed\n");
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} else {
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puts("memory test done\n");
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}
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#endif /* DEBUG */
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#ifdef CONFIG_SPL_BSS_DRAM_START
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extern char __bss_dram_start[];
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extern char __bss_dram_end[];
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memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
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#endif
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}
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void board_init_f(ulong dummy)
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{
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/* Set the stack pointer. */
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asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* Set global data pointer. */
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gd = &gdata;
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board_inithw();
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board_init_r(NULL, 0);
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}
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u32 spl_boot_device(void)
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{
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return CONFIG_SPL_BOOT_DEVICE;
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}
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#ifdef CONFIG_SPL_BLOCK_SUPPORT
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void spl_block_device_init(void)
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{
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ide_init();
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return (serial_tstc() && serial_getc() == 'c');
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}
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#endif
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void spl_display_print(void)
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{
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/* print a hint, so that we will not use the wrong SPL by mistake */
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puts(" Boot device: " BOOT_DEVICE_TYPE "\n" );
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}
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void lowlevel_init(void)
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{
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}
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#ifdef USE_DL_PREFIX
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/* quick and dirty memory allocation */
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static ulong next_mem = CONFIG_SPL_MALLOC_START;
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void *memalign(size_t alignment, size_t bytes)
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{
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ulong mem = ALIGN(next_mem, alignment);
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next_mem = mem + bytes;
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if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
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printf("spl: out of memory\n");
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hang();
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}
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return (void *)mem;
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}
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void free(void* mem)
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{
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}
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#endif
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#endif /* CONFIG_SPL_BUILD */
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int board_early_init_f(void)
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{
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return 0;
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}
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#define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
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#define STATIC_READ_CYCLE_SHIFT 0
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#define STATIC_DELAYED_OE (1 << 7)
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#define STATIC_WRITE_CYCLE_SHIFT 8
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#define STATIC_WRITE_PULSE_SHIFT 16
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#define STATIC_WRITE_BURST_EN (1 << 23)
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#define STATIC_TURN_AROUND_SHIFT 24
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#define STATIC_BUFFER_PRESENT (1 << 28)
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#define STATIC_READ_BURST_EN (1 << 29)
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#define STATIC_BUS_WIDTH8 (0 << 30)
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#define STATIC_BUS_WIDTH16 (1 << 30)
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#define STATIC_BUS_WIDTH32 (2 << 30)
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void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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if (ctrl & NAND_CTRL_CHANGE) {
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nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
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if (ctrl & NAND_CLE)
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nandaddr |= BIT(NAND_CLE_ADDR_PIN);
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else if (ctrl & NAND_ALE)
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nandaddr |= BIT(NAND_ALE_ADDR_PIN);
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this->IO_ADDR_W = (void __iomem *) nandaddr;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, (void __iomem *) nandaddr);
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}
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
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int nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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udelay(chip->chip_delay);
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return 1;
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}
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void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i;
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struct nand_chip *chip = mtd->priv;
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for (i = 0; i < len; i++)
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buf[i] = readb(chip->IO_ADDR_R);
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}
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void nand_dev_reset(struct nand_chip *chip)
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{
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writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
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udelay(chip->chip_delay);
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writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
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while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
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;
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}
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}
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#else
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#define nand_dev_reset(chip) /* framework will reset the chip anyway */
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#define nand_read_buf NULL /* framework will provide a default one */
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#define nand_dev_ready NULL /* dev_ready is optional */
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#endif
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int board_nand_init(struct nand_chip *chip)
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{
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/* Block reset Static core */
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reset_block(SYS_CTRL_RST_STATIC, 1);
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reset_block(SYS_CTRL_RST_STATIC, 0);
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/* Enable clock to Static core */
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enable_clock(SYS_CTRL_CLK_STATIC);
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/* enable flash support on static bus.
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* Enable static bus onto GPIOs, only CS0 */
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pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
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pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
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pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
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pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
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pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
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pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
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pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
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pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
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pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
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pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
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pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
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pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
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pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
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/* Setup the static bus CS0 to access FLASH */
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writel((0x3f << STATIC_READ_CYCLE_SHIFT)
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| (0x3f << STATIC_WRITE_CYCLE_SHIFT)
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| (0x1f << STATIC_WRITE_PULSE_SHIFT)
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| (0x03 << STATIC_TURN_AROUND_SHIFT) |
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STATIC_BUS_WIDTH16,
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STATIC_CTL_BANK0);
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chip->cmd_ctrl = nand_hwcontrol;
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->chip_delay = 30;
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chip->dev_ready = nand_dev_ready;
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chip->read_buf = nand_read_buf;
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nand_dev_reset(chip);
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
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/* assume uart is already initialized by SPL */
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#if defined(CONFIG_START_IDE)
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puts("IDE: ");
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ide_init();
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#endif
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return 0;
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}
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/* copied from board/evb64260/sdram_init.c */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int *base, long int maxsize)
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{
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volatile long int *addr, *b = base;
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long int cnt, val, save1, save2;
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#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
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for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
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cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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save1 = *addr; /* save contents of addr */
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save2 = *b; /* save contents of base */
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*addr = cnt; /* write cnt to addr */
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*b = 0; /* put null at base */
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/* check at base address */
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if ((*b) != 0) {
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*addr = save1; /* restore *addr */
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*b = save2; /* restore *b */
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return (0);
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}
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val = *addr; /* read *addr */
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*addr = save1;
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*b = save2;
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if (val != cnt) {
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/* fix boundary condition.. STARTVAL means zero */
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if (cnt == STARTVAL / sizeof (long))
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cnt = 0;
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return (cnt * sizeof (long));
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}
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}
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return maxsize;
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}
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int dram_init(void)
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{
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gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_SDRAM_SIZE);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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u32 value;
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/* set the pin multiplexers to enable talking to Ethernent Phys */
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pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
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pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
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// Ensure the MAC block is properly reset
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reset_block(SYS_CTRL_RST_MAC, 1);
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udelay(10);
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reset_block(SYS_CTRL_RST_MAC, 0);
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// Enable the clock to the MAC block
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enable_clock(SYS_CTRL_CLK_MAC);
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value = readl(SYS_CTRL_GMAC_CTRL);
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/* Use simple mux for 25/125 Mhz clock switching */
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value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
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/* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
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value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
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/* set auto tx speed */
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value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
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writel(value, SYS_CTRL_GMAC_CTRL);
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return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
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}
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