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openwrt_deco_e4r/target/linux/coldfire/patches/004-MCF54418-support-in-Linux-2.6.38.patch

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From b23f9dc392de5be8a2bc17342d6aee49208a80d8 Mon Sep 17 00:00:00 2001
From: Alison Wang <b18965@freescale.com>
Date: Thu, 4 Aug 2011 09:59:39 +0800
Subject: [PATCH 04/52] MCF54418 support in Linux 2.6.38
Add MCF54418 support in Linux 2.6.38.
Signed-off-by: Alison Wang <b18965@freescale.com>
---
arch/m68k/coldfire/m5441x/Makefile | 38 +
arch/m68k/coldfire/m5441x/config.c | 604 +++++++++++++
arch/m68k/coldfire/m5441x/devices.c | 787 +++++++++++++++++
arch/m68k/configs/m54418twr_defconfig | 1244 +++++++++++++++++++++++++++
arch/m68k/include/asm/cf_5441x_cacheflush.h | 527 ++++++++++++
arch/m68k/include/asm/mcf5441x_ccm.h | 157 ++++
arch/m68k/include/asm/mcf5441x_clock.h | 22 +
arch/m68k/include/asm/mcf5441x_dspi.h | 671 +++++++++++++++
arch/m68k/include/asm/mcf5441x_dtim.h | 95 ++
arch/m68k/include/asm/mcf5441x_edma.h | 303 +++++++
arch/m68k/include/asm/mcf5441x_eport.h | 94 ++
arch/m68k/include/asm/mcf5441x_fbcs.h | 204 +++++
arch/m68k/include/asm/mcf5441x_flexcan.h | 139 +++
arch/m68k/include/asm/mcf5441x_gpio.h | 509 +++++++++++
arch/m68k/include/asm/mcf5441x_intc.h | 727 ++++++++++++++++
arch/m68k/include/asm/mcf5441x_pm.h | 33 +
arch/m68k/include/asm/mcf5441x_rtc.h | 127 +++
arch/m68k/include/asm/mcf5441x_scm.h | 33 +
arch/m68k/include/asm/mcf5441x_sdramc.h | 141 +++
arch/m68k/include/asm/mcf5441x_xbs.h | 77 ++
20 files changed, 6532 insertions(+), 0 deletions(-)
create mode 100644 arch/m68k/coldfire/m5441x/Makefile
create mode 100644 arch/m68k/coldfire/m5441x/config.c
create mode 100644 arch/m68k/coldfire/m5441x/devices.c
create mode 100644 arch/m68k/configs/m54418twr_defconfig
create mode 100644 arch/m68k/include/asm/cf_5441x_cacheflush.h
create mode 100644 arch/m68k/include/asm/mcf5441x_ccm.h
create mode 100644 arch/m68k/include/asm/mcf5441x_clock.h
create mode 100644 arch/m68k/include/asm/mcf5441x_dspi.h
create mode 100644 arch/m68k/include/asm/mcf5441x_dtim.h
create mode 100644 arch/m68k/include/asm/mcf5441x_edma.h
create mode 100644 arch/m68k/include/asm/mcf5441x_eport.h
create mode 100644 arch/m68k/include/asm/mcf5441x_fbcs.h
create mode 100644 arch/m68k/include/asm/mcf5441x_flexcan.h
create mode 100644 arch/m68k/include/asm/mcf5441x_gpio.h
create mode 100644 arch/m68k/include/asm/mcf5441x_intc.h
create mode 100644 arch/m68k/include/asm/mcf5441x_pm.h
create mode 100644 arch/m68k/include/asm/mcf5441x_rtc.h
create mode 100644 arch/m68k/include/asm/mcf5441x_scm.h
create mode 100644 arch/m68k/include/asm/mcf5441x_sdramc.h
create mode 100644 arch/m68k/include/asm/mcf5441x_xbs.h
--- /dev/null
+++ b/arch/m68k/coldfire/m5441x/Makefile
@@ -0,0 +1,38 @@
+#
+# Makefile for Linux arch/m68k/coldfire/m5441x source directory
+#
+
+obj-$(CONFIG_M5441X) += devices.o config.o
+
+ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
+ obj-y += usb.o
+endif
+ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),)
+ifeq ($(strip $(CONFIG_USB_M5441X_FSLS)),)
+ obj-y += usb_dr.o
+endif
+endif
+
+#ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
+ifneq ($(strip $(CONFIG_USB_OTG) $(CONFIG_USB_M5441X_MAX3353_FSLS)),)
+ obj-y += xcvr.o
+endif
+ifneq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)), )
+ obj-y += max3353_xc.o
+ifneq ($(strip $(CONFIG_USB_OTG)),)
+ obj-m += max3353_otg.o
+endif
+endif
+
+# USB Host controller support
+ifneq ($(strip $(CONFIG_USB_M5441X_H1)),)
+ obj-y += usb_host.o xcvr_host.o
+endif
+
+ifneq ($(CONFIG_FEC),)
+obj-y += fec.o
+endif
+
+ifneq ($(CONFIG_MODELO_SWITCH),)
+obj-y += l2switch.o
+endif
--- /dev/null
+++ b/arch/m68k/coldfire/m5441x/config.c
@@ -0,0 +1,604 @@
+/*
+ * linux/arch/m68k/coldfire/m5441x/config.c
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/clockchips.h>
+#include <linux/delay.h>
+#include <asm/bootinfo.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/cfcache.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/cfmmu.h>
+#include <asm/setup.h>
+#include <asm/irq.h>
+#include <asm/traps.h>
+#include <asm/movs.h>
+#include <asm/movs.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/cf-sram.h>
+
+#include <asm/mcfsim.h>
+
+#define UBOOT_EXTRA_CLOCKS
+#include <asm/bootinfo.h>
+
+#include <asm/mcf5441x_intc.h>
+#include <asm/mcf5441x_sdramc.h>
+#include <asm/mcf5441x_fbcs.h>
+#include <asm/mcf5441x_dtim.h>
+#include <asm/mcf5441x_xbs.h>
+
+extern int get_irq_list(struct seq_file *p, void *v);
+extern char _text, _end;
+extern char _etext, _edata, __init_begin, __init_end;
+extern struct console mcfrs_console;
+extern char m68k_command_line[CL_SIZE];
+extern unsigned long availmem;
+extern unsigned long shadow_cacr;
+EXPORT_SYMBOL(shadow_cacr);
+extern struct mem_info m68k_ramdisk;
+
+static int irq_enable[NR_IRQS];
+unsigned long num_pages;
+
+/* cf dma physical addresses */
+unsigned long cf_dma_base;
+EXPORT_SYMBOL(cf_dma_base);
+unsigned long cf_dma_end;
+EXPORT_SYMBOL(cf_dma_end);
+unsigned long cf_dma_size;
+EXPORT_SYMBOL(cf_dma_size);
+
+/* ethernet mac addresses from uboot */
+unsigned char uboot_enet0[6];
+unsigned char uboot_enet1[6];
+
+void coldfire_sort_memrec(void)
+{
+ int i, j;
+
+ /* Sort the m68k_memory records by address */
+ for (i = 0; i < m68k_num_memory; ++i) {
+ for (j = i + 1; j < m68k_num_memory; ++j) {
+ if (m68k_memory[i].addr > m68k_memory[j].addr) {
+ struct mem_info tmp;
+ tmp = m68k_memory[i];
+ m68k_memory[i] = m68k_memory[j];
+ m68k_memory[j] = tmp;
+ }
+ }
+ }
+ /* Trim off discontiguous bits */
+ for (i = 1; i < m68k_num_memory; ++i) {
+ if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
+ m68k_memory[i].addr) {
+ printk(KERN_DEBUG "m68k_parse_bootinfo: "
+ "addr gap between 0x%lx & 0x%lx\n",
+ m68k_memory[i-1].addr+m68k_memory[i-1].size,
+ m68k_memory[i].addr);
+ m68k_num_memory = i;
+ break;
+ }
+ }
+}
+
+/*
+ * UBoot Handler
+ */
+int __init uboot_commandline(char *bootargs)
+{
+ int len = 0, cmd_line_len;
+ static struct uboot_record uboot_info;
+ u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
+
+ extern unsigned long uboot_info_stk;
+
+ /* validate address */
+ if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
+ (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
+ return 0;
+
+ /* Add offset to get post-remapped kernel memory location */
+ uboot_info.bdi = (struct bd_info *)
+ ((*(u32 *)(uboot_info_stk)) + offset);
+ uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
+ uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
+ uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
+ uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
+
+#if defined(CONFIG_BLK_DEV_INITRD)
+ m68k_ramdisk.addr = uboot_info.initrd_start;
+ m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ?
+ (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0;
+#endif
+
+ /* copy over mac addresses */
+ memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
+ memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
+
+ /* copy command line */
+ cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
+ if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
+ len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
+ cmd_line_len);
+
+ return len;
+}
+
+#define DEFAULT_COMMAND_LINE \
+ "debug root=/dev/nfs rw \
+ nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \
+ ip=172.27.155.51:172.27.155.1"
+
+/*
+ * Early Coldfire Initialization.
+ */
+asmlinkage void __init cf_early_init(void)
+{
+ SET_VBR((void *)MCF_RAMBAR1);
+
+ /* Mask all interrupts */
+ MCF_INTC0_IMRL = 0xFFFFFFFF;
+ MCF_INTC0_IMRH = 0xFFFFFFFF;
+ MCF_INTC1_IMRL = 0xFFFFFFFF;
+ MCF_INTC1_IMRH = 0xFFFFFFFF;
+
+#if defined(CONFIG_USB)
+ /* reset USB3300 */
+ asm ("moveb #0x40, %%d0\n\t"
+ "moveb %%d0, 0xec090000\n\t"
+ : : : "%d0");
+ mdelay(1);
+ asm ("moveb #0x0, %%d0\n\t"
+ "moveb %%d0, 0xec090000\n\t"
+ : : : "%d0");
+#endif
+
+#if defined(CONFIG_NOR_FLASH_BASE)
+ MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
+#else
+ MCF_FBCS_CSAR(1) = 0x00000000;
+#endif
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ MCF_FBCS_CSAR(0) = FLEXBUS_LCD_CMD_ADDRESS;
+ MCF_FBCS_CSMR(0) = MCF_FBCS_CSMR_BAM_128K | MCF_FBCS_CSMR_V;
+ MCF_FBCS_CSCR(0) = MCF_FBCS_CSCR_BLS | MCF_FBCS_CSCR_AA |
+ MCF_FBCS_CSCR_PS_16;
+#endif
+
+#if CONFIG_SDRAM_SIZE > (256*1024*1024)
+ /* Init optional SDRAM chip select */
+ MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
+#endif
+
+ MCF_XBS_CRS2 = 0x100;
+ /* Setup SDRAM crossbar(XBS) priorities */
+ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/
+ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/
+ MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/
+ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/
+ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/
+ MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/
+ MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/
+
+ m68k_machtype = MACH_CFMMU;
+ m68k_fputype = FPU_CFV4E;
+ m68k_mmutype = MMU_CFV4E;
+ m68k_cputype = CPU_CFV4E;
+
+ /* initialize PHYSRAM */
+ m68k_num_memory = 0;
+ m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */
+ m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
+
+ if (!uboot_commandline(m68k_command_line)) {
+#if defined(CONFIG_BOOTPARAM)
+ strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
+#else
+ strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
+#endif
+ }
+
+ /* Invalidate caches via CACR */
+ flush_bcache();
+ cacr_set(CACHE_DISABLE_MODE);
+
+ /* Turn on caches via CACR, enable EUSP */
+ cacr_set(CACHE_INITIAL_MODE);
+}
+
+/* Assembler routines */
+asmlinkage void buserr(void);
+asmlinkage void trap(void);
+asmlinkage void system_call(void);
+asmlinkage void inthandler(void);
+
+void __init coldfire_trap_init(void)
+{
+ int i = 0;
+ e_vector *vectors;
+
+ vectors = (e_vector *)MCF_RAMBAR1;
+ /*
+ * There is a common trap handler and common interrupt
+ * handler that handle almost every vector. We treat
+ * the system call and bus error special, they get their
+ * own first level handlers.
+ */
+ for (i = 3; (i <= 23); i++)
+ vectors[i] = trap;
+ for (i = 33; (i <= 63); i++)
+ vectors[i] = trap;
+ for (i = 24; (i <= 31); i++)
+ vectors[i] = inthandler;
+ for (i = 64; (i < 255); i++)
+ vectors[i] = inthandler;
+
+ vectors[255] = 0;
+ vectors[2] = buserr;
+ vectors[32] = system_call;
+}
+
+void settimericr(unsigned int timer, unsigned int level)
+{
+ volatile unsigned char *icrp;
+ unsigned int icr = 0;
+ unsigned char irq = 0;
+
+ if (timer <= 3) {
+ switch (timer) {
+ case 0:
+ irq = 32;
+ icr = MCFSIM_ICR_TIMER0;
+ break;
+ case 1:
+ irq = 33;
+ icr = MCFSIM_ICR_TIMER1;
+ break;
+ case 2:
+ irq = 34;
+ icr = MCFSIM_ICR_TIMER2;
+ break;
+ case 3:
+ irq = 35;
+ icr = MCFSIM_ICR_TIMER3;
+ break;
+ }
+
+ icrp = (volatile unsigned char *) (icr);
+ *icrp = level;
+ coldfire_enable_irq0(irq);
+ }
+}
+
+void coldfire_sched_clk_init(void);
+
+void coldfire_tick(void)
+{
+ /* Reset the ColdFire timer */
+ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER);
+}
+
+void __init coldfire_sched_init(irq_handler_t handler)
+{
+ unsigned int mcf_timerlevel = 5;
+ unsigned int mcf_timervector = 64+32;
+
+ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR);
+ __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR);
+ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
+ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
+ MCF_DTIM0_DTMR);
+
+ request_irq(mcf_timervector, handler, IRQF_DISABLED, \
+ "timer", (void *)MCF_DTIM0_DTMR);
+
+ settimericr(0, mcf_timerlevel);
+
+ /* initialize the fast clock */
+ coldfire_sched_clk_init();
+}
+
+int timerirqpending(int timer)
+{
+ unsigned int imr = 0;
+ unsigned ret = 0;
+
+ switch (timer) {
+ case 1:
+ imr = 0x1;
+ break;
+ case 2:
+ imr = 0x2;
+ break;
+ default:
+ break;
+ }
+
+ ret = getiprh() & imr;
+ return ret;
+}
+
+unsigned long coldfire_gettimeoffset(void)
+{
+ volatile unsigned long trr, tcn, offset;
+
+ tcn = __raw_readw(MCF_DTIM0_DTCN);
+ trr = __raw_readl(MCF_DTIM0_DTRR);
+ offset = (tcn * (1000000 / HZ)) / trr;
+
+ /* Check if we just wrapped the counters and maybe missed a tick */
+ if ((offset < (1000000 / HZ / 2)) && timerirqpending(1))
+ offset += 1000000 / HZ;
+ return offset;
+}
+
+/* sched_clock support */
+
+static unsigned long long sched_clk_val;
+
+static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev)
+{
+ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER);
+ sched_clk_val += 0x100000000LL;
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Setup DTIM3 as the 5441x sched_clock() implementation. The
+ * input frequency to the clock is the internal bus clock (MCF_BUSCLK)
+ * which is the system clock (MCF_CLK) / 2.
+ *
+ * On a system running at 266Mhz:
+ * MCF_CLK = 266Mhz (266000000)
+ * MCF_BUSCLK = 133Mhz (133000000)
+ * DTIM3 Tick = 133Mhz (133000000)
+ * Tick Resolution = 7.5ns (round to 8ns/Tick)
+ *
+ * On a system running at 240Mhz:
+ * MCF_CLK = 240Mhz (240000000)
+ * MCF_BUSCLK = 120Mhz (120000000)
+ * DTIM3 Tick = 120Mhz (120000000)
+ * Tick Resolution = 8.4ns (round to 8ns/Tick)
+ */
+void __init coldfire_sched_clk_init(void)
+{
+ unsigned int mcf_timerlevel = 5;
+ unsigned int mcf_timervector = 64+32+3; /* DTIM3 */
+
+ printk(KERN_INFO "Initializing DTIM3 for sched_clock\n");
+ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR);
+ __raw_writel(0xffffffff, MCF_DTIM3_DTRR);
+ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \
+ MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR);
+
+ sched_clk_val = 0;
+ request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \
+ "timer", (void *)MCF_DTIM3_DTMR);
+
+ settimericr(3, mcf_timerlevel);
+}
+
+#ifndef CONFIG_GENERIC_CLOCKEVENTS
+/* get highres timer */
+unsigned long long sched_clock(void)
+{
+ unsigned long long ret = 0;
+ ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN));
+ ret = ret << 3;
+ return ret;
+}
+
+#else /*CONFIG_GENERIC_CLOCKEVENTS*/
+
+static unsigned long long sched_dtim_clk_val;
+
+unsigned long long sched_clock(void)
+{
+ unsigned long flags;
+ unsigned long long tcn, cycles;
+
+ local_irq_save(flags);
+ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
+ cycles = sched_dtim_clk_val;
+ local_irq_restore(flags);
+ return cycles + tcn;
+}
+
+unsigned long long sys_dtim2_read(void)
+{
+ unsigned long flags;
+ unsigned long long tcn, cycles;
+
+ local_irq_save(flags);
+ tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
+ cycles = sched_dtim_clk_val;
+ local_irq_restore(flags);
+
+ return cycles + tcn;
+}
+
+static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)dev;
+
+ __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER);
+ sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ;
+ evt->event_handler(evt);
+ return IRQ_HANDLED;
+}
+
+void sys_dtim2_init(struct clock_event_device *evt)
+{
+ unsigned int mcf_timerlevel = 5;
+ unsigned int mcf_timervector = 64+32+2; /* DTIM2 */
+
+ printk(KERN_INFO "Initializing DTIM2 for sched_clock\n");
+ __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR);
+ __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR);
+ __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
+ MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
+ MCF_DTIM2_DTMR);
+
+ request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \
+ "timer2", (void *)evt);
+
+ settimericr(3, mcf_timerlevel);
+ return;
+}
+
+#endif
+
+void coldfire_reboot(void)
+{
+ /* disable interrupts and do a software reset */
+ asm("movew #0x2700, %%sr\n\t"
+ "moveb #0x40, %%d0\n\t"
+ "moveb %%d0, 0xec090000\n\t"
+ : : : "%d0");
+
+ mdelay(10);
+
+ asm("moveb #0xc0, %%d0\n\t"
+ "moveb %%d0, 0xec090000\n\t"
+ : : : "%d0");
+}
+
+static void coldfire_get_model(char *model)
+{
+ sprintf(model, "Version 4 ColdFire");
+}
+
+/*
+ * Setup the nodes and the boot memory.
+ *
+ * memory_start and memory_end are VIRTUAL addresses
+ */
+static void __init
+coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
+{
+ unsigned long base_pfn;
+
+ /* compute total pages in system */
+ num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
+
+ /* align start/end to page boundries */
+ memory_start = PAGE_ALIGN(memory_start);
+ memory_end = memory_end & PAGE_MASK;
+
+ /* page numbers */
+ base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
+ min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
+ max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
+
+ high_memory = (void *)memory_end;
+ availmem = memory_start;
+
+ /* setup bootmem data */
+ m68k_setup_node(0);
+ availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
+ base_pfn, max_low_pfn);
+ availmem = PAGE_ALIGN(availmem);
+
+ printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n",
+ availmem, __pa(availmem));
+ printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n",
+ memory_start, memory_end);
+ printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n",
+ base_pfn, min_low_pfn, max_low_pfn);
+
+ /* turn over physram */
+ free_bootmem(__pa(availmem), memory_end - availmem);
+
+ /* configure physical dma area */
+ cf_dma_base = __pa(PAGE_ALIGN(memory_start));
+ cf_dma_size = CONFIG_DMA_SIZE;
+ cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1;
+
+ printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n",
+ cf_dma_base, cf_dma_end, CONFIG_DMA_BASE);
+
+ printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n",
+ MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS));
+}
+
+/*
+ * Architecture setup for Coldfire
+ */
+void __init config_coldfire(void)
+{
+ unsigned long endmem, startmem;
+
+ /*
+ * Calculate endmem from m68k_memory[0] assuming that a single
+ * chunk of ram is being configured.
+ */
+ startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
+ endmem = PAGE_OFFSET + m68k_memory[0].size;
+
+ /* set virt to node shift to be the high nibble byte */
+ m68k_virt_to_node_shift = 28;
+
+ printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
+ size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
+
+ memset(irq_enable, 0, sizeof(irq_enable));
+
+/* JKM -- moved early*/
+/*register_console(&mcfrs_console);*/
+
+ /*
+ * Setup coldfire mach-specific handlers
+ */
+ mach_max_dma_address = 0xffffffff;
+ mach_sched_init = coldfire_sched_init;
+ mach_tick = coldfire_tick;
+ mach_gettimeoffset = coldfire_gettimeoffset;
+ mach_reset = coldfire_reboot;
+ mach_get_model = coldfire_get_model;
+
+ coldfire_bootmem_alloc(startmem, endmem-1);
+
+#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
+ conswitchp = &dummy_con;
+#endif
+
+#if defined(CONFIG_SERIAL_COLDFIRE)
+ /*
+ * This causes trouble when it is re-registered later.
+ * Currently this is fixed by conditionally commenting
+ * out the register_console in mcf_serial.c
+ */
+/*JKM -- moved earlier*/
+ register_console(&mcfrs_console);
+#endif
+}
+
+#ifdef CONFIG_SRAM
+static int __init setup_sram_pool(void)
+{
+ declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE);
+ return 0;
+}
+postcore_initcall(setup_sram_pool);
+#endif
--- /dev/null
+++ b/arch/m68k/coldfire/m5441x/devices.c
@@ -0,0 +1,787 @@
+/*
+ * Coldfire M5441x Platform Device Configuration
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Lanttor.Guo@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/mtd/partitions.h>
+#ifdef CONFIG_MMC_SPI
+#include <linux/mmc/host.h>
+#include <linux/spi/mmc_spi.h>
+#endif
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfqspi.h>
+#include <asm/mcfdspi.h>
+#include <asm/cf_io.h>
+
+/*
+ * I2C: only support i2c0 module on m5441x platform
+ */
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+static struct resource coldfire_i2c_resources[] = {
+ { /* I/O */
+ .start = 0xFC058000,
+ .end = 0xFC058010,
+ .flags = IORESOURCE_MEM,
+ },
+ { /* IRQ */
+ .start = (64 + 30),
+ .end = (64 + 30),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device coldfire_i2c_device = {
+ .name = "mcf-i2c",
+ .id = 0, /*bus number*/
+ .num_resources = ARRAY_SIZE(coldfire_i2c_resources),
+ .resource = coldfire_i2c_resources,
+};
+
+static void mcf5441x_init_i2c(void)
+{
+ MCF_PM_PPMCR0 = 22;
+ platform_device_register(&coldfire_i2c_device);
+}
+
+#ifdef CONFIG_I2C_BOARDINFO
+static struct i2c_board_info mcf_i2c_devices[] = {
+#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
+ {
+ I2C_BOARD_INFO("max3353", 0x2c),
+ },
+#endif
+};
+#endif
+
+#endif
+
+#if defined(CONFIG_MMC_ESDHC)
+static struct resource sd_mmc_esdhc_resources[] = {
+ [0] = {
+ .name = "esdhc-module",
+ .start = 0xFC0CC000,
+ .end = 0xFC0CC000 + 0x100,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "esdhc-int-level",
+ .start = (64 + 64 + 64 + 31),
+ .end = (64 + 64 + 64 + 31),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .name = "esdhc-pin",
+ .start = &MCF_GPIO_PAR_ESDHCH,
+ .end = &MCF_GPIO_PAR_ESDHCL,
+ .flags = IORESOURCE_MEM,
+ },
+ [3] = {
+ .name = "esdhc-slew",
+ .start = &MCF_GPIO_SRCR_SDHC,
+ .end = &MCF_GPIO_SRCR_SDHC,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device sd_mmc_esdhc_device = {
+ .name = "esdhc",
+ .id = -1,
+ .resource = sd_mmc_esdhc_resources,
+ .num_resources = ARRAY_SIZE(sd_mmc_esdhc_resources),
+};
+#endif
+
+#if defined(CONFIG_MTD_NAND_FSL_NFC)
+static struct resource nfc_resources[] = {
+ [0] = {
+ .name = "nfc-config",
+ .start = 0xFC0FC000,
+ .end = 0xFC0FFF3B,
+ .flags = IORESOURCE_MEM,
+
+ },
+ [1] = {
+ .name = "nfc-int-level",
+ .start = (64 + 64 + 64 + 25),
+ .end = (64 + 64 + 64 + 25),
+ .flags = IORESOURCE_IRQ,
+ },
+
+};
+static struct platform_device nfc_device = {
+ .name = "fsl_nfc",
+ .id = -1,
+ .resource = nfc_resources,
+ .num_resources = ARRAY_SIZE(nfc_resources),
+};
+#endif
+
+/*
+ * DSPI
+ */
+#ifdef CONFIG_SPI
+
+#if defined(CONFIG_DSPI0) /* DSPI0 initialization */
+#define M5441X_DSPI0_MCR 0xFC05C000 /* base */
+
+#define M5441X_DSPI0_IRQ_SOURCE (31)
+#define M5441X_DSPI0_IRQ_VECTOR (64 + M5441X_DSPI0_IRQ_SOURCE)
+
+/* number of supported SPI selects */
+#define SPI_NUM_CHIPSELECTS 8
+
+#define M5441X_SPI0_PAR_VAL (MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK | \
+ MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | \
+ MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN | \
+ MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0)
+
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition at26df081a_partitions[] = {
+ {
+ .name = "at26df081a",
+ .size = (1024*64*16),
+ .offset = 0x00000000,
+ .mask_flags = 0,
+ }
+};
+#endif
+
+#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+static struct flash_platform_data at26df081a_platform_data = {
+ .name = "Atmel at26df081a SPI Flash chip",
+#ifdef CONFIG_MTD_PARTITIONS
+ .parts = at26df081a_partitions,
+ .nr_parts =
+ sizeof(at26df081a_partitions) / sizeof(*at26df081a_partitions),
+#endif
+ .type = "at26df081a"
+};
+
+static struct coldfire_dspi_chip at26df081a_chip_info = {
+ .mode = SPI_MODE_0,
+ .bits_per_word = 16, /* How many bits per word to transfer
+ per one time (8 or 16) */
+ .void_write_data = 0,
+ .dbr = 0,
+ .pbr = 0,
+ .br = 0,
+ .pcssck = 1,
+ .pasc = 1,
+ .pdt = 1,
+ .cssck = 4,
+ .asc = 4,
+ .dt = 14,
+};
+#endif
+
+#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE)
+static struct fsl_ssd1289_fb_display fsl_ssd1289_data = {
+ .width = 320,
+ .height = 240,
+ .xres = 320,
+ .yres = 240,
+ .bpp = 16,
+};
+#endif
+
+#if defined(CONFIG_SSD1289_SPI_MODE)
+static struct coldfire_dspi_chip ssd1289_chip_info = {
+ .mode = SPI_MODE_0,
+ .bits_per_word = 9,
+ .void_write_data = 0,
+ .dbr = 0,
+ .pbr = 0,
+ .br = 1,
+ .pcssck = 0,
+ .pasc = 0,
+ .pdt = 0,
+ .cssck = 0,
+ .asc = 0,
+ .dt = 0,
+};
+#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct coldfire_dspi_chip spidev_chip_info = {
+ .bits_per_word = 8,
+};
+#endif
+
+
+static struct coldfire_spi_master spi0_master_info = {
+ .bus_num = 1,
+ .num_chipselect = SPI_NUM_CHIPSELECTS,
+ .irq_list = 0, /* not used */
+ .irq_source = M5441X_DSPI0_IRQ_SOURCE,
+ .irq_vector = M5441X_DSPI0_IRQ_VECTOR,
+ .irq_mask = (1 << M5441X_DSPI0_IRQ_SOURCE),
+ .irq_lp = 0x2, /* irq level */
+ .par_val = M5441X_SPI0_PAR_VAL,
+ .cs_control = NULL,
+};
+
+static struct resource coldfire_spi0_resources[] = {
+ [0] = {
+ .name = "spi-par",
+ .start = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */
+ .end = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */
+ .flags = IORESOURCE_MEM
+ },
+
+ [1] = {
+ .name = "spi-module",
+ .start = M5441X_DSPI0_MCR, /* DSPI MCR Base */
+ .end = M5441X_DSPI0_MCR + 0xc0, /* DSPI mem map end */
+ .flags = IORESOURCE_MEM
+ },
+
+ [2] = {
+ .name = "spi-int-level",
+ .start = (u32)&MCF_INTC0_ICR31, /* ICR start */
+ .end = (u32)&MCF_INTC0_ICR31, /* ICR end */
+ .flags = IORESOURCE_MEM
+ },
+
+ [3] = {
+ .name = "spi-int-mask",
+ .start = (u32)&MCF_INTC0_IMRL, /* IMRL */
+ .end = (u32)&MCF_INTC0_IMRL, /* IMRL */
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct platform_device coldfire_spi0 = {
+ .name = "spi_coldfire",
+ .id = -1,
+ .resource = coldfire_spi0_resources,
+ .num_resources = ARRAY_SIZE(coldfire_spi0_resources),
+ .dev = {
+ .platform_data = &spi0_master_info,
+ }
+};
+
+#elif defined(CONFIG_DSPI1) /* DSPI1 initialization */
+#define M5441X_DSPI1_MCR 0xFC03C000 /* base */
+
+#define M5441X_DSPI1_IRQ_SOURCE (54)
+#define M5441X_DSPI1_IRQ_VECTOR (64 + 64 + M5441X_DSPI1_IRQ_SOURCE)
+
+/* number of supported SPI selects */
+#define SPI_NUM_CHIPSELECTS 8
+
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct coldfire_dspi_chip spidev_chip_info = {
+ .bits_per_word = 8,
+};
+#endif
+
+static struct coldfire_spi_master spi1_master_info = {
+ .bus_num = 1,
+ .num_chipselect = SPI_NUM_CHIPSELECTS,
+ .irq_list = 0, /* not used */
+ .irq_source = M5441X_DSPI1_IRQ_SOURCE,
+ .irq_vector = M5441X_DSPI1_IRQ_VECTOR,
+ .irq_mask = (1 << (M5441X_DSPI1_IRQ_SOURCE - 32)),
+ .irq_lp = 0x2, /* irq level */
+ .cs_control = NULL,
+};
+
+static struct resource coldfire_spi1_resources[] = {
+ [0] = {
+ .name = "spi-par",
+ .start = (u32)&MCF_GPIO_PAR_ESDHCH, /* PAR_ESDHCH */
+ .end = (u32)&MCF_GPIO_PAR_ESDHCL, /* PAR_ESDHCL */
+ .flags = IORESOURCE_MEM
+ },
+
+ [1] = {
+ .name = "spi-module",
+ .start = M5441X_DSPI1_MCR, /* DSPI MCR Base */
+ .end = M5441X_DSPI1_MCR + 0xc0, /* DSPI mem map end */
+ .flags = IORESOURCE_MEM
+ },
+
+ [2] = {
+ .name = "spi-int-level",
+ .start = (u32)&MCF_INTC1_ICR54, /* ICR start */
+ .end = (u32)&MCF_INTC1_ICR54, /* ICR end */
+ .flags = IORESOURCE_MEM
+ },
+
+ [3] = {
+ .name = "spi-int-mask",
+ .start = (u32)&MCF_INTC1_IMRH, /* IMRL */
+ .end = (u32)&MCF_INTC1_IMRH, /* IMRL */
+ .flags = IORESOURCE_MEM
+ }
+};
+
+static struct platform_device coldfire_spi1 = {
+ .name = "spi_coldfire",
+ .id = -1,
+ .resource = coldfire_spi1_resources,
+ .num_resources = ARRAY_SIZE(coldfire_spi1_resources),
+ .dev = {
+ .platform_data = &spi1_master_info,
+ }
+};
+
+#ifdef CONFIG_MMC_SPI
+static struct coldfire_dspi_chip dspi_sd_chip_info = {
+ .mode = SPI_MODE_0,
+ .bits_per_word = 8,
+ .void_write_data = 0xff,
+ .dbr = 0,
+ .pbr = 1,
+ .br = 1,
+ .pcssck = 2,
+ .pasc = 2,
+ .pdt = 2,
+ .cssck = 5,
+ .asc = 5,
+ .dt = 5,
+};
+
+int mmc_spi_init(struct device *mmc_spi_device,
+ irqreturn_t mmc_spi_irq_handler(int irq, void *private),
+ void *irq_privatedata)
+{
+ int ret;
+#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1)
+ int card_detect_extern_irq = 64 + 1;
+ /*this is irq1 hardware work round*/
+ MCF_GPIO_PAR_IRQ0H |= 0x3;
+
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1;
+
+ MCF_INTC0_ICR1 = 7; /* IRQ1 */
+#if debug_mmc_spi
+ printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x "
+ "MCF_EPORT_EPFR %x MCF_EPORT_EPIER %x "
+ "MCF_INTC0_IMRL %x MCF_INTC0_INTFRCL %x "
+ "MCF_INTC0_IPRL %x\n",
+ MCF_INTC0_ICR1, MCF_EPORT_EPPAR, MCF_EPORT_EPFR,
+ MCF_EPORT_EPIER, MCF_INTC0_IMRL, MCF_INTC0_INTFRCL,
+ MCF_INTC0_IPRL);
+#endif
+#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7)
+ int card_detect_extern_irq = 64 + 7;
+ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
+
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
+
+ MCF_INTC0_ICR7 = 2; /* IRQ7 */
+#ifdef debug_mmc_spi
+ printk("MCF_INTC0_ICR7 %x MCF_EPORT_EPPAR %x\n",
+ MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
+#endif
+#else
+ int card_detect_extern_irq = 64 + 7;
+ MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
+
+ MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
+ MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
+
+ MCF_INTC0_ICR7 = 2; /* IRQ7 */
+#ifdef debug_mmc_spi
+ printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x\n",
+ MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
+#endif
+#endif
+
+ ret = request_irq(card_detect_extern_irq,
+ mmc_spi_irq_handler, IRQF_DISABLED,
+ "mmc_spi_irq", irq_privatedata);
+ if (ret) {
+ printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret);
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static struct mmc_spi_platform_data mcf5441x_mmc_pdata = {
+ .ocr_mask = MMC_VDD_33_34,
+ .init = mmc_spi_init,
+};
+#endif
+
+#endif
+
+/* DSPI device */
+static struct spi_board_info spi_board_info[] = {
+
+#if defined(CONFIG_DSPI1) && defined(CONFIG_MMC_SPI)
+ {
+ .modalias = "mmc_spi",
+ .max_speed_hz = 50000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = &mcf5441x_mmc_pdata,
+ .controller_data = &dspi_sd_chip_info,
+ },
+#endif
+#if defined(CONFIG_DSPI0) && (defined(CONFIG_MTD_M25P80) || \
+ defined(CONFIG_MTD_M25P80_MODULE))
+ {
+ .modalias = "m25p80", /* Name of spi driver for this device */
+ .max_speed_hz = 70000000, /* max spi clock in HZ */
+ .bus_num = 1,
+ .chip_select = CONFIG_DSP0_SBF_CS,
+ .platform_data = &at26df081a_platform_data,
+ .controller_data = &at26df081a_chip_info
+ },
+#endif
+
+#if defined(CONFIG_DSPI0) && defined(CONFIG_SSD1289_SPI_MODE)
+ {
+ .modalias = "spi-ssd1289",
+ .max_speed_hz = 50000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = &fsl_ssd1289_data,
+ .controller_data = &ssd1289_chip_info
+ },
+#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
+ .bus_num = 1,
+ .chip_select = 0, /* CS0 */
+ .controller_data = &spidev_chip_info,
+ },
+#endif
+};
+
+/*
+ * m5441x_spi_init - Initialize SPI
+ */
+static int __init m5441x_spi_init(void)
+{
+ int retval;
+
+ /* register device */
+#if defined(CONFIG_DSPI0)
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SCK_MASK) |
+ MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK;
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) |
+ MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT;
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) |
+ MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN;
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_PCS0_MASK) |
+ MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0;
+ MCF_GPIO_PAR_DSPI0WL = 0x80;
+ retval = platform_device_register(&coldfire_spi0);
+ if (retval < 0)
+ goto out;
+#elif defined(CONFIG_DSPI1)
+ MCF_PM_PPMCR0 = 0xf;
+ MCF_GPIO_PAR_ESDHCH = 0x55; /* DAT[3:0] */
+ MCF_GPIO_PAR_ESDHCL = 0x05; /* CMD, CLK */
+ MCF_GPIO_SRCR_IRQ0 = 3;
+ MCF_GPIO_SRCR_SDHC = 3;
+ retval = platform_device_register(&coldfire_spi1);
+ if (retval < 0)
+ goto out;
+#endif
+
+ /* register board info */
+ if (ARRAY_SIZE(spi_board_info))
+ retval = spi_register_board_info(spi_board_info,
+ ARRAY_SIZE(spi_board_info));
+
+out:
+ return retval;
+}
+#endif
+
+#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
+/*
+ * UART initialization
+ */
+static struct mcf_platform_uart m5441x_uart_platform[] = {
+#ifdef CONFIG_SERIAL_MCF_UART0
+ {
+ .mapbase = MCFUART_BASE0,
+ .irq = MCFINT0_VECBASE + MCFINT_UART0,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART1
+ {
+ .mapbase = MCFUART_BASE1,
+ .irq = MCFINT0_VECBASE + MCFINT_UART1,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART2
+ {
+ .mapbase = MCFUART_BASE2,
+ .irq = MCFINT0_VECBASE + MCFINT_UART2,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART3
+ {
+ .mapbase = MCFUART_BASE3,
+ .irq = MCFINT0_VECBASE + MCFINT_UART3,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART4
+ {
+ .mapbase = MCFUART_BASE4,
+ .irq = MCFINT1_VECBASE + MCFINT_UART4,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART5
+ {
+ .mapbase = MCFUART_BASE5,
+ .irq = MCFINT1_VECBASE + MCFINT_UART5,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART6
+ {
+ .mapbase = MCFUART_BASE6,
+ .irq = MCFINT1_VECBASE + MCFINT_UART6,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART7
+ {
+ .mapbase = MCFUART_BASE7,
+ .irq = MCFINT1_VECBASE + MCFINT_UART7,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART8
+ {
+ .mapbase = MCFUART_BASE8,
+ .irq = MCFINT1_VECBASE + MCFINT_UART8,
+ },
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART9
+ {
+ .mapbase = MCFUART_BASE9,
+ .irq = MCFINT1_VECBASE + MCFINT_UART9,
+ },
+#endif
+ {}
+};
+
+static struct platform_device m5441x_uart = {
+ .name = "mcfuart",
+ .id = 0,
+ .dev.platform_data = m5441x_uart_platform,
+};
+
+static void m5441x_uarts_init(void)
+{
+#ifdef CONFIG_SERIAL_MCF_UART0
+ /* enable uart0 clock */
+ MCF_PM_PPMCR0 = 24;
+ /* gpio pin assignment for uart0 */
+ MCF_GPIO_PAR_UART0 =
+ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RXD_MASK) |
+ MCF_GPIO_PAR_UART0_U0RXD_U0RXD;
+ MCF_GPIO_PAR_UART0 =
+ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0TXD_MASK) |
+ MCF_GPIO_PAR_UART0_U0TXD_U0TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART1
+ /* enable uart1 clock */
+ MCF_PM_PPMCR0 = 25;
+ /* gpio pin assignment for uart1 */
+ MCF_GPIO_PAR_UART1 =
+ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RXD_MASK) |
+ MCF_GPIO_PAR_UART1_U1RXD_U1RXD;
+ MCF_GPIO_PAR_UART1 =
+ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1TXD_MASK) |
+ MCF_GPIO_PAR_UART1_U1TXD_U1TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART2
+ /* enable uart2 clock */
+ MCF_PM_PPMCR0 = 26;
+ /* gpio pin assignment for uart2 */
+ MCF_GPIO_PAR_UART2 =
+ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RXD_MASK) |
+ MCF_GPIO_PAR_UART2_U2RXD_U2RXD;
+ MCF_GPIO_PAR_UART2 =
+ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2TXD_MASK) |
+ MCF_GPIO_PAR_UART2_U2TXD_U2TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART3
+ /* enable uart3 clock */
+ MCF_PM_PPMCR0 = 27;
+ /* gpio pin assignment for uart3 */
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) |
+ MCF_GPIO_PAR_DSPI0_SIN_U3RXD;
+ MCF_GPIO_PAR_DSPI0WH =
+ (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) |
+ MCF_GPIO_PAR_DSPI0_SOUT_U3TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART4
+ /* enable uart4 clock */
+ MCF_PM_PPMCR1 = 24;
+ /* gpio pin assignment for uart4 */
+ MCF_GPIO_PAR_UART0 =
+ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RTS_MASK) |
+ MCF_GPIO_PAR_UART0_U0RTS_U4RXD;
+ MCF_GPIO_PAR_UART0 =
+ (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0CTS_MASK) |
+ MCF_GPIO_PAR_UART0_U0CTS_U4TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART5
+ /* enable uart5 clock */
+ MCF_PM_PPMCR1 = 25;
+ /* gpio pin assignment for uart5 */
+ MCF_GPIO_PAR_UART1 =
+ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RTS_MASK) |
+ MCF_GPIO_PAR_UART1_U1RTS_U5RXD;
+ MCF_GPIO_PAR_UART1 =
+ (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1CTS_MASK) |
+ MCF_GPIO_PAR_UART1_U1CTS_U5TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART6
+ /* enable uart6 clock */
+ MCF_PM_PPMCR1 = 26;
+ /* gpio pin assignment for uart6 */
+ MCF_GPIO_PAR_UART2 =
+ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RTS_MASK) |
+ MCF_GPIO_PAR_UART2_U2RTS_U6RXD;
+ MCF_GPIO_PAR_UART2 =
+ (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2CTS_MASK) |
+ MCF_GPIO_PAR_UART2_U2CTS_U6TXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART7
+ /* enable uart7 clock */
+ MCF_PM_PPMCR1 = 27;
+ /* gpio pin assignment for uart7 */
+ MCF_GPIO_PAR_SSI0H &= (MCF_GPIO_PAR_SSI0H_FS_MASK);
+ MCF_GPIO_PAR_SSI0H |= (MCF_GPIO_PAR_SSI0H_FS_U7TXD);
+ MCF_GPIO_PAR_SSI0L &= (MCF_GPIO_PAR_SSI0L_BCLK_MASK);
+ MCF_GPIO_PAR_SSI0L |= (MCF_GPIO_PAR_SSI0L_BCLK_U7RXD);
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART8
+ /* enable uart8 clock */
+ MCF_PM_PPMCR1 = 28;
+ /* gpio pin assignment for uart8 */
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) |
+ MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD;
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) |
+ MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD;
+#endif
+#ifdef CONFIG_SERIAL_MCF_UART9
+ /* enable uart4 clock */
+ MCF_PM_PPMCR1 = 29;
+ /* gpio pin assignment for uart9 */
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1TX_MASK) |
+ MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD;
+ MCF_GPIO_PAR_CANI2C =
+ (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1RX_MASK) |
+ MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD;
+#endif
+}
+#endif
+
+#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
+/*
+ * RTC initialization
+ */
+static struct platform_device rtc_device = {
+ .name = "rtc-m5441x",
+ .id = -1,
+};
+
+static void m5441x_rtc_init(void)
+{
+ /* Power management: enable RTC clock */
+ MCF_PM_PPMCR0 = 42;
+}
+#endif
+
+
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+static struct platform_device fsl_ssd1289_device = {
+ .name = "fsl-ssd1289",
+ .id = -1,
+ .dev = {
+ .platform_data = &fsl_ssd1289_data,
+ },
+};
+#endif
+
+static struct platform_device *m5441x_devices[] __initdata = {
+#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
+ &m5441x_uart,
+#endif
+#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
+ &rtc_device,
+#endif
+#if defined(CONFIG_MMC_ESDHC)
+ &sd_mmc_esdhc_device,
+#endif
+#if defined(CONFIG_MTD_NAND_FSL_NFC)
+ &nfc_device,
+#endif
+#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
+ &fsl_ssd1289_device,
+#endif
+};
+
+static int __init mcf5441x_init_devices(void)
+{
+ printk(KERN_INFO "mcf5441x_init_devices: %s.\n", __func__);
+
+#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
+#ifdef CONFIG_I2C_BOARDINFO
+ i2c_register_board_info(0, mcf_i2c_devices,
+ ARRAY_SIZE(mcf_i2c_devices));
+#endif
+ mcf5441x_init_i2c();
+#endif
+#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE)
+ m5441x_spi_init();
+#endif
+#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
+ m5441x_uarts_init();
+#endif
+#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
+ m5441x_rtc_init();
+#endif
+ platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
+ return 0;
+}
+
+arch_initcall(mcf5441x_init_devices);
+
+
--- /dev/null
+++ b/arch/m68k/configs/m54418twr_defconfig
@@ -0,0 +1,1244 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29
+# Fri Apr 23 14:36:43 2010
+#
+CONFIG_M68K=y
+CONFIG_MMU=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+# CONFIG_TIME_LOW_RES is not set
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_NO_IOPORT is not set
+# CONFIG_NO_DMA is not set
+CONFIG_HZ=100
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBD=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# Platform dependent setup
+#
+CONFIG_COLDFIRE=y
+CONFIG_CFV4E=y
+# CONFIG_FPU is not set
+# CONFIG_AMIGA is not set
+# CONFIG_ATARI is not set
+# CONFIG_MAC is not set
+# CONFIG_APOLLO is not set
+# CONFIG_VME is not set
+# CONFIG_HP300 is not set
+# CONFIG_SUN3X is not set
+# CONFIG_Q40 is not set
+# CONFIG_SUN3 is not set
+
+#
+# Processor type
+#
+# CONFIG_M68020 is not set
+# CONFIG_M68030 is not set
+# CONFIG_M68040 is not set
+# CONFIG_M68060 is not set
+# CONFIG_M5445X is not set
+CONFIG_HAVE_FSL_USB_DR=y
+# CONFIG_M547X_8X is not set
+CONFIG_M5441X=y
+CONFIG_M54418=y
+CONFIG_M54418EVB=y
+CONFIG_MCFCLK=250000000
+# CONFIG_MCF_USER_HALT is not set
+CONFIG_MMU_CFV4E=y
+CONFIG_SDRAM_BASE=0x40000000
+CONFIG_SDRAM_SIZE=0x08000000
+CONFIG_NOR_FLASH_BASE=0x00000000
+CONFIG_DMA_BASE=0xdf000000
+CONFIG_DMA_SIZE=0x1000000
+# CONFIG_VDSO is not set
+# CONFIG_M68KFPU_EMU is not set
+CONFIG_ADVANCED=y
+# CONFIG_RMW_INSNS is not set
+CONFIG_SINGLE_MEMORY_CHUNK=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+
+#
+# General setup
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_PROC_HARDWARE=y
+CONFIG_ZONE_DMA=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_KLIPS is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_NAND_FSL_NFC=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=64000
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BROADCOM5222_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+CONFIG_NATIONAL8364x_PHY=y
+CONFIG_NATIONAL8384x_PHY=y
+CONFIG_MicrelKSZ8041_PHY=y
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+CONFIG_FEC=y
+CONFIG_FEC2=y
+CONFIG_FEC_SHARED_PHY=y
+# CONFIG_MODELO_SWITCH is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_COLDFIRE_IRDA is not set
+# CONFIG_SERIAL_COLDFIRE_EDMA is not set
+CONFIG_SERIAL_MCF=y
+CONFIG_SERIAL_MCF_BAUDRATE=115200
+CONFIG_SERIAL_MCF_CONSOLE=y
+CONFIG_SERIAL_MCF_UART0=y
+# CONFIG_SERIAL_MCF_UART1 is not set
+# CONFIG_SERIAL_MCF_UART2 is not set
+# CONFIG_SERIAL_MCF_UART3 is not set
+# CONFIG_SERIAL_MCF_UART4 is not set
+# CONFIG_SERIAL_MCF_UART5 is not set
+# CONFIG_SERIAL_MCF_UART6 is not set
+# CONFIG_SERIAL_MCF_UART7 is not set
+# CONFIG_SERIAL_MCF_UART8 is not set
+# CONFIG_SERIAL_MCF_UART9 is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+CONFIG_SPI_DSPI=y
+# CONFIG_SPI_COLDFIRE_DSPI_EDMA is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_COLDFIRE_WATCHDOG=y
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_FSL=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_M5445X_ULPI is not set
+# CONFIG_USB_M5445X_FSLS is not set
+CONFIG_USB_M5441X_ULPI=y
+# CONFIG_USB_M5441X_FSLS is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+CONFIG_USB_GADGET_FSL_USB2=y
+CONFIG_USB_FSL_USB2=m
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_FILE_STORAGE_TEST=y
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_ESDHC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_MCF is not set
+CONFIG_RTC_M5441X=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+CONFIG_COLDFIRE_EDMA=y
+CONFIG_COLDFIRE_EDMA_TEST=m
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# Character devices
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=y
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V3 is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_BOOTPARAM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+
+#
+# OCF Configuration
+#
+# CONFIG_OCF_OCF is not set
+
+#
+# Talitos Driver
+#
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_MCFCAU is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--- /dev/null
+++ b/arch/m68k/include/asm/cf_5441x_cacheflush.h
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Based on include/asm-m68k/cacheflush.h
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef M68K_CF_5441x_CACHEFLUSH_H
+#define M68K_CF_5441x_CACHEFLUSH_H
+
+#include <asm/cfcache.h>
+
+/*
+ * Coldfire Cache Model
+ *
+ * The Coldfire processors use a Harvard architecture cache configured
+ * as four-way set associative. The cache does not implement bus snooping
+ * so cache coherency with other masters must be maintained in software.
+ *
+ * The cache is managed via the CPUSHL instruction in conjunction with
+ * bits set in the CACR (cache control register). Currently the code
+ * uses the CPUSHL enhancement which adds the ability to
+ * invalidate/clear/push a cacheline by physical address. This feature
+ * is designated in the Hardware Configuration Register [D1-CPES].
+ *
+ * CACR Bits:
+ * DPI[28] cpushl invalidate disable for d-cache
+ * IDPI[12] cpushl invalidate disable for i-cache
+ * SPA[14] cpushl search by physical address
+ * IVO[20] cpushl invalidate only
+ *
+ * Random Terminology:
+ * * invalidate = reset the cache line's valid bit
+ * * push = generate a line-sized store of the data if its contents are
+ * marked as modifed (the modified flag is cleared after
+ * the store)
+ * * clear = push + invalidate
+ */
+
+/**
+ * flush_icache - Flush all of the instruction cache
+ */
+static inline void flush_icache(void)
+{
+ asm volatile("nop\n"
+ "moveq%.l #0,%%d0\n"
+ "moveq%.l #0,%%d1\n"
+ "move%.l %%d0,%%a0\n"
+ "1:\n"
+ "cpushl %%ic,(%%a0)\n"
+ "add%.l #0x0010,%%a0\n"
+ "addq%.l #1,%%d1\n"
+ "cmpi%.l %0,%%d1\n"
+ "bne 1b\n"
+ "moveq%.l #0,%%d1\n"
+ "addq%.l #1,%%d0\n"
+ "move%.l %%d0,%%a0\n"
+ "cmpi%.l #4,%%d0\n"
+ "bne 1b\n"
+ : : "i" (CACHE_SETS)
+ : "a0", "d0", "d1");
+}
+
+/**
+ * flush_dcache - Flush all of the data cache
+ */
+static inline void flush_dcache(void)
+{
+ asm volatile("nop\n"
+ "moveq%.l #0,%%d0\n"
+ "moveq%.l #0,%%d1\n"
+ "move%.l %%d0,%%a0\n"
+ "1:\n"
+ "cpushl %%dc,(%%a0)\n"
+ "add%.l #0x0010,%%a0\n"
+ "addq%.l #1,%%d1\n"
+ "cmpi%.l %0,%%d1\n"
+ "bne 1b\n"
+ "moveq%.l #0,%%d1\n"
+ "addq%.l #1,%%d0\n"
+ "move%.l %%d0,%%a0\n"
+ "cmpi%.l #4,%%d0\n"
+ "bne 1b\n"
+ : : "i" (CACHE_SETS)
+ : "a0", "d0", "d1");
+}
+
+/**
+ * flush_bcache - Flush all of both caches
+ */
+static inline void flush_bcache(void)
+{
+ asm volatile("nop\n"
+ "moveq%.l #0,%%d0\n"
+ "moveq%.l #0,%%d1\n"
+ "move%.l %%d0,%%a0\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "add%.l #0x0010,%%a0\n"
+ "addq%.l #1,%%d1\n"
+ "cmpi%.l %0,%%d1\n"
+ "bne 1b\n"
+ "moveq%.l #0,%%d1\n"
+ "addq%.l #1,%%d0\n"
+ "move%.l %%d0,%%a0\n"
+ "cmpi%.l #4,%%d0\n"
+ "bne 1b\n"
+ : : "i" (CACHE_SETS)
+ : "a0", "d0", "d1");
+}
+
+/**
+ * cf_cache_clear - invalidate cache
+ * @paddr: starting physical address
+ * @len: number of bytes
+ *
+ * Invalidate cache lines starting at paddr for len bytes.
+ * Those lines are not pushed.
+ */
+static inline void cf_cache_clear(unsigned long paddr, int len)
+{
+ /* number of lines */
+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
+ if (len == 0)
+ return;
+
+ /* align on set boundary */
+ paddr &= 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%d0\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "subq%.l #1,%%d0\n"
+ "bne%.b 1b\n"
+ "movec %2,%%cacr\n"
+ : : "a" (paddr), "r" (len),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA+CF_CACR_IVO)
+ : "a0", "d0");
+}
+
+/**
+ * cf_cache_push - Push dirty cache out with no invalidate
+ * @paddr: starting physical address
+ * @len: number of bytes
+ *
+ * Push the any dirty lines starting at paddr for len bytes.
+ * Those lines are not invalidated.
+ */
+static inline void cf_cache_push(unsigned long paddr, int len)
+{
+ /* number of lines */
+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
+ if (len == 0)
+ return;
+
+ /* align on set boundary */
+ paddr &= 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%d0\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "subq%.l #1,%%d0\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : : "a" (paddr), "r" (len),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
+ : "a0", "d0");
+}
+
+/**
+ * cf_cache_flush - Push dirty cache out and invalidate
+ * @paddr: starting physical address
+ * @len: number of bytes
+ *
+ * Push the any dirty lines starting at paddr for len bytes and
+ * invalidate those lines.
+ */
+static inline void cf_cache_flush(unsigned long paddr, int len)
+{
+ /* number of lines */
+ len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
+ if (len == 0)
+ return;
+
+ /* align on set boundary */
+ paddr &= 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%d0\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "subq%.l #1,%%d0\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : : "a" (paddr), "r" (len),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA)
+ : "a0", "d0");
+}
+
+/**
+ * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
+ * @vstart - starting virtual address
+ * @vend: ending virtual address
+ *
+ * Push the any dirty data/instr lines starting at paddr for len bytes and
+ * invalidate those lines.
+ */
+static inline void cf_cache_flush_range(unsigned long vstart,
+ unsigned long vend)
+{
+ int len;
+
+ /* align on set boundary */
+ vstart &= 0xfffffff0;
+ vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
+ len = vend - vstart;
+ if (len == 0)
+ return;
+ vstart = __pa(vstart);
+ vend = vstart + len;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%a1\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "cmpa%.l %%a0,%%a1\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : /* no return */
+ : "a" (vstart), "a" (vend),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA)
+ : "a0", "a1", "d0");
+}
+
+/**
+ * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
+ * @vstart - starting virtual address
+ * @vend: ending virtual address
+ *
+ * Push/Clear the virtual range *vstart* -> *vend* using the enhanced
+ * cpushl instruction to search by physical address.
+ *
+ * Assumes CACR[IVO] is 0
+ * CACR[DDPI] is 0
+ *
+ * Sets CACR[SPA] to 1 for the duration of this routine
+ */
+static inline void cf_dcache_flush_range(unsigned long vstart,
+ unsigned long vend)
+{
+ /* align on set boundary */
+ vstart &= 0xfffffff0;
+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%a1\n"
+ "1:\n"
+ "cpushl %%dc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "cmpa%.l %%a0,%%a1\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : /* no return */
+ : "a" (__pa(vstart)), "a" (__pa(vend)),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA)
+ : "a0", "a1", "d0");
+}
+
+/**
+ * cf_dcache_inv_range - Invalidate data cache in range
+ * @vstart - starting virtual address
+ * @vend: ending virtual address
+ *
+ * Invalidate the virtual range *vstart* -> *vend* using the enhanced
+ * cpushl instruction to search by physical address.
+ *
+ * Assumes CACR[DDPI] is 0
+ *
+ * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine
+ */
+static inline void cf_dcache_inv_range(unsigned long vstart,
+ unsigned long vend)
+{
+ /* align on set boundary */
+ vstart &= 0xfffffff0;
+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%a1\n"
+ "1:\n"
+ "cpushl %%dc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "cmpa%.l %%a0,%%a1\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : /* no return */
+ : "a" (__pa(vstart)), "a" (__pa(vend)),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA | CF_CACR_IVO)
+ : "a0", "a1", "d0");
+}
+
+/**
+ * cf_dcache_push_range - Push data cache in range
+ * @vstart - starting virtual address
+ * @vend: ending virtual address
+ *
+ * Push the virtual range *vstart* -> *vend* using the enhanced
+ * cpushl instruction to search by physical address.
+ *
+ * Assumes CACR[IVO] is 0
+ *
+ * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine
+ */
+static inline void cf_dcache_push_range(unsigned long vstart,
+ unsigned long vend)
+{
+ /* align on set boundary */
+ vstart &= 0xfffffff0;
+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%a1\n"
+ "1:\n"
+ "cpushl %%dc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "cmpa%.l %%a0,%%a1\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : /* no return */
+ : "a" (__pa(vstart)), "a" (__pa(vend)),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA | CF_CACR_DPI)
+ : "a0", "a1", "d0");
+}
+
+/**
+ * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
+ * @vstart - starting virtual address
+ * @vend: ending virtual address
+ *
+ * Push the any dirty instr lines starting at paddr for len bytes and
+ * invalidate those lines. This should just be an invalidate since you
+ * shouldn't be able to have dirty instruction cache.
+ */
+static inline void cf_icache_flush_range(unsigned long vstart,
+ unsigned long vend)
+{
+ /* align on set boundary */
+ vstart &= 0xfffffff0;
+ vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
+
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%a0\n"
+ "move%.l %1,%%a1\n"
+ "1:\n"
+ "cpushl %%ic,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "cmpa%.l %%a0,%%a1\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : /* no return */
+ : "a" (__pa(vstart)), "a" (__pa(vend)),
+ "r" (shadow_cacr),
+ "i" (CF_CACR_SPA)
+ : "a0", "a1", "d0");
+}
+
+/**
+ * flush_cache_mm - Flush an mm_struct
+ * @mm: mm_struct to flush
+ */
+static inline void flush_cache_mm(struct mm_struct *mm)
+{
+ if (mm == current->mm)
+ flush_bcache();
+}
+
+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+
+/**
+ * flush_cache_range - Flush a cache range
+ * @vma: vma struct
+ * @start: Starting address
+ * @end: Ending address
+ *
+ * flush_cache_range must be a macro to avoid a dependency on
+ * linux/mm.h which includes this file.
+ */
+static inline void flush_cache_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ if (vma->vm_mm == current->mm)
+ cf_cache_flush_range(start, end);
+}
+
+/**
+ * flush_cache_page - Flush a page of the cache
+ * @vma: vma struct
+ * @vmaddr:
+ * @pfn: page numer
+ *
+ * flush_cache_page must be a macro to avoid a dependency on
+ * linux/mm.h which includes this file.
+ */
+static inline void flush_cache_page(struct vm_area_struct *vma,
+ unsigned long vmaddr, unsigned long pfn)
+{
+ if (vma->vm_mm == current->mm)
+ cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
+}
+
+/**
+ * __flush_page_to_ram - Push a page out of the cache
+ * @vaddr: Virtual address at start of page
+ *
+ * Push the page at kernel virtual address *vaddr* and clear
+ * the icache.
+ */
+static inline void __flush_page_to_ram(void *vaddr)
+{
+ asm volatile("nop\n"
+ "move%.l %2,%%d0\n"
+ "or%.l %3,%%d0\n"
+ "movec %%d0,%%cacr\n"
+ "move%.l %0,%%d0\n"
+ "and%.l #0xfffffff0,%%d0\n"
+ "move%.l %%d0,%%a0\n"
+ "move%.l %1,%%d0\n"
+ "1:\n"
+ "cpushl %%bc,(%%a0)\n"
+ "lea 0x10(%%a0),%%a0\n"
+ "subq%.l #1,%%d0\n"
+ "bne.b 1b\n"
+ "movec %2,%%cacr\n"
+ : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
+ "r" (shadow_cacr), "i" (CF_CACR_SPA)
+ : "a0", "d0");
+}
+
+/*
+ * Various defines for the kernel.
+ */
+
+extern void cache_clear(unsigned long paddr, int len);
+extern void cache_push(unsigned long paddr, int len);
+extern void flush_icache_range(unsigned long address, unsigned long endaddr);
+
+#define flush_cache_all() flush_bcache()
+#define flush_cache_vmap(start, end) flush_bcache()
+#define flush_cache_vunmap(start, end) flush_bcache()
+
+#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend)
+#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+
+#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
+
+/**
+ * copy_to_user_page - Copy memory to user page
+ */
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ memcpy(dst, src, len);
+ cf_cache_flush(page_to_phys(page), PAGE_SIZE);
+}
+
+/**
+ * copy_from_user_page - Copy memory from user page
+ */
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr,
+ void *dst, void *src, int len)
+{
+ cf_cache_flush(page_to_phys(page), PAGE_SIZE);
+ memcpy(dst, src, len);
+}
+
+#endif /* M68K_CF_5441x_CACHEFLUSH_H */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_ccm.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_CCM_H__
+#define __MCF5441X_CCM_H__
+
+/*********************************************************************
+*
+* Chip Configuration Module (CCM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
+#define MCF_CCM_CCR MCF_REG16(0xEC090004)
+/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
+#define MCF_CCM_RCON MCF_REG16(0xEC090008)
+/* Chip Identification Register (Read-only) */
+#define MCF_CCM_CIR MCF_REG16(0xEC09000A)
+/* Miscellaneous Control Register */
+#define MCF_CCM_MISCCR MCF_REG16(0xEC09000E)
+#define MCF_CCM_CDRH MCF_REG16(0xEC090010) /* Clock Divider Register */
+#define MCF_CCM_CDRL MCF_REG16(0xEC090012) /* Clock Divider Register */
+/* USB On-the-Go Controller Status Register */
+#define MCF_CCM_UOCSR MCF_REG16(0xEC090014)
+/* USB On-the-Go Controller Status Register */
+#define MCF_CCM_UHCSR MCF_REG16(0xEC090016)
+/* Miscellaneous Control Register */
+#define MCF_CCM_MISCCR3 MCF_REG16(0xEC090018)
+/* Miscellaneous Control Register */
+#define MCF_CCM_MISCCR2 MCF_REG16(0xEC09001A)
+#define MCF_CCM_ADCTSR MCF_REG16(0xEC09001C)
+#define MCF_CCM_DACTSR MCF_REG16(0xEC09001E)
+/* Serial Boot Facility Status Register (Read Only) */
+#define MCF_CCM_SBFSR MCF_REG16(0xEC090020)
+/* Serial Boot Facility Control Register */
+#define MCF_CCM_SBFCR MCF_REG16(0xEC090022)
+#define MCF_CCM_FNACR MCF_REG16(0xEC090024)
+
+/* Bit definitions and macros for CIR */
+/* Part revision number */
+#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F))
+/* Part identification number */
+#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
+#define MCF_CCM_CIR_PRN_MASK (0x003F)
+#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6)
+#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6)
+#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6)
+#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6)
+#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6)
+
+/* Bit definitions and macros for MISCCR */
+/* Part revision number */
+#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F))
+/* Part identification number */
+#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
+#define MCF_CCM_CIR_PRN_MASK (0x003F)
+#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6)
+#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6)
+#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6)
+#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6)
+#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6)
+#define MCF_CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
+#define MCF_CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
+#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
+#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
+#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
+#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
+#define MCF_CCM_MISCCR_LIMP (0x1000)
+#define MCF_CCM_MISCCR_BME (0x0800)
+#define MCF_CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
+#define MCF_CCM_MISCCR_BMT_MASK (0xF8FF)
+#define MCF_CCM_MISCCR_BMT_65536 (0)
+#define MCF_CCM_MISCCR_BMT_32768 (1)
+#define MCF_CCM_MISCCR_BMT_16384 (2)
+#define MCF_CCM_MISCCR_BMT_8192 (3)
+#define MCF_CCM_MISCCR_BMT_4096 (4)
+#define MCF_CCM_MISCCR_BMT_2048 (5)
+#define MCF_CCM_MISCCR_BMT_1024 (6)
+#define MCF_CCM_MISCCR_BMT_512 (7)
+#define MCF_CCM_MISCCR_SDHCSRC (0x0040)
+#define MCF_CCM_MISCCR_SSI1SRC (0x0020)
+#define MCF_CCM_MISCCR_SSI0SRC (0x0010)
+#define MCF_CCM_MISCCR_USBHOC (0x0008)
+#define MCF_CCM_MISCCR_USBOOC (0x0004)
+#define MCF_CCM_MISCCR_USBPUE (0x0002)
+#define MCF_CCM_MISCCR_USBSRC (0x0001)
+#define MCF_CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
+#define MCF_CCM_CDRH_SSI0DIV_MASK (0x00FF)
+#define MCF_CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
+#define MCF_CCM_CDRH_SSI1DIV_MASK (0xFF00)
+#define MCF_CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
+#define MCF_CCM_CDRL_LPDIV_MASK (0xFF0F)
+#define MCF_CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
+
+#define MCF_CCM_UOCSR_DPPD (0x2000)
+#define MCF_CCM_UOCSR_DMPD (0x1000)
+#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
+#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
+#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
+#define MCF_CCM_UOCSR_DPPU (0x0100)
+#define MCF_CCM_UOCSR_AVLD (0x0080)
+#define MCF_CCM_UOCSR_BVLD (0x0040)
+#define MCF_CCM_UOCSR_VVLD (0x0020)
+#define MCF_CCM_UOCSR_SEND (0x0010)
+#define MCF_CCM_UOCSR_PWRFLT (0x0008)
+#define MCF_CCM_UOCSR_WKUP (0x0004)
+#define MCF_CCM_UOCSR_UOMIE (0x0002)
+#define MCF_CCM_UOCSR_XPDE (0x0001)
+
+#define MCF_CCM_UHCSR_DRV_VBUS (0x0010)
+#define MCF_CCM_UHCSR_PWRFLT (0x0008)
+#define MCF_CCM_UHCSR_WKUP (0x0004)
+#define MCF_CCM_UHCSR_UOMIE (0x0002)
+#define MCF_CCM_UHCSR_XPDE (0x0001)
+
+#define MCF_CCM_MISCCR3_TMR_ENET (0x1000)
+#define MCF_CCM_MISCCR3_ENETCLK(x) ((((x)&7))<<8)
+#define MCF_CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
+#define MCF_CCM_MISCCR3_ENETCLK_MII (0x0700)
+#define MCF_CCM_MISCCR3_ENETCLK_OSC (0x0600)
+#define MCF_CCM_MISCCR3_ENETCLK_USB (0x0500)
+#define MCF_CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
+#define MCF_CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
+#define MCF_CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
+#define MCF_CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
+#define MCF_CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
+
+#define MCF_CCM_MISCCR2_EXTCLKBYP (0x0800)
+#define MCF_CCM_MISCCR2_DDR2CLK (0x0400)
+#define MCF_CCM_MISCCR2_RGPIO_HALF (0x0200)
+#define MCF_CCM_MISCCR2_SWTSCR (0x0100)
+#define MCF_CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
+#define MCF_CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
+#define MCF_CCM_MISCCR2_DCCBYP (0x0080)
+#define MCF_CCM_MISCCR2_DAC1SEL (0x0040)
+#define MCF_CCM_MISCCR2_DAC0SEL (0x0020)
+#define MCF_CCM_MISCCR2_ADCEN (0x0010)
+#define MCF_CCM_MISCCR2_ADC7SEL (0x0008)
+#define MCF_CCM_MISCCR2_ADC3SEL (0x0004)
+#define MCF_CCM_MISCCR2_FBHALF (0x0002)
+#define MCF_CCM_MISCCR2_ULPI (0x0001)
+
+#define MCF_CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
+#define MCF_CCM_FNACR_PCR_MASK (0xF0FFFFFF)
+#define MCF_CCM_FNACR_MCC(x) ((x)&0xFFFF)
+#define MCF_CCM_FNACR_MCC_MASK (0xFFFF0000)
+
+#endif /* __MCF5445X_CCM_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_clock.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_CLOCK_H__
+#define __MCF5441X_CLOCK_H__
+
+#define MCF_PLL_CR MCF_REG32(0xFC000000)
+#define MCF_PLL_DR MCF_REG32(0xFC000004)
+#define MCF_PLL_SR MCF_REG32(0xFC000008)
+
+#define MCF_PLL_DR_OUTDIV4 0x001F0000
+#define MCF_PLL_DR_OUTDIV1 0x1F
+
+
+#endif /*__MCF5441X_CLOCK_H__*/
+
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_dspi.h
@@ -0,0 +1,671 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Lanttor.Guo@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_DSPI_H__
+#define __MCF5441X_DSPI_H__
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+/* DSPI Module Configuration Register */
+#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000)
+#define MCF_DSPI1_DMCR MCF_REG32(0xFC03C000)
+/* DSPI Transfer Count Register */
+#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008)
+#define MCF_DSPI1_DTCR MCF_REG32(0xFC03C008)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C)
+#define MCF_DSPI1_DCTAR0 MCF_REG32(0xFC03C00C)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024)
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028
+/* DSPI Status Register */
+#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C)
+#define MCF_DSPI1_DSR MCF_REG32(0xFC03C02C)
+/* DSPI DMA/Interrupt Request Select and Enable Register */
+#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030)
+#define MCF_DSPI1_DRSER MCF_REG32(0xFC03C030)
+/* DSPI Transmit FIFO Register */
+#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034)
+#define MCF_DSPI1_DTFR MCF_REG32(0xFC03C034)
+/* DSPI Receive FIFO Register */
+#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038)
+#define MCF_DSPI1_DRFR MCF_REG32(0xFC03C038)
+/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C)
+/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040)
+/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044)
+/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048)
+/* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C)
+/* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080)
+/* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084)
+/* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088)
+
+/* Parameterized register read/write macros for multiple registers */
+/* DSPI Clock and Transfer Attributes Register */
+#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004))
+/* DSPI Transmit FIFO Debugging Registers */
+#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004))
+/* DSPI Receive FIFO Debugging Registers */
+#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004))
+
+/* Bit definitions and macros for DMCR */
+/* Halt -- stops and starts DSPI transfers */
+#define MCF_DSPI_DMCR_HALT (0x00000001)
+/* Sample point selection */
+#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8)
+/* Clear receive FIFO */
+#define MCF_DSPI_DMCR_CLRRXF (0x00000400)
+/* Clear transmit FIFO */
+#define MCF_DSPI_DMCR_CLRTXF (0x00000800)
+/* Disable receive FIFO */
+#define MCF_DSPI_DMCR_DISRXF (0x00001000)
+/* Disable transmit FIFO */
+#define MCF_DSPI_DMCR_DISTXF (0x00002000)
+/* Module Disable */
+#define MCF_DSPI_DMCR_MDIS (0x00004000)
+/* Peripheral chip-select 0 inactive state */
+#define MCF_DSPI_DMCR_PCSIS0 (0x00010000)
+/* Peripheral chip-select 1 inactive state */
+#define MCF_DSPI_DMCR_PCSIS1 (0x00020000)
+/* Peripheral chip-select 2 inactive state */
+#define MCF_DSPI_DMCR_PCSIS2 (0x00040000)
+/* Peripheral chip-select 3 inactive state */
+#define MCF_DSPI_DMCR_PCSIS3 (0x00080000)
+/* Peripheral chip-select 4 inactive state */
+#define MCF_DSPI_DMCR_PCSIS4 (0x00100000)
+/* Peripheral chip-select 5 inactive state */
+#define MCF_DSPI_DMCR_PCSIS5 (0x00200000)
+/* Peripheral chip-select 6 inactive state */
+#define MCF_DSPI_DMCR_PCSIS6 (0x00400000)
+/* Peripheral chip-select 7 inactive state */
+#define MCF_DSPI_DMCR_PCSIS7 (0x00800000)
+/* Receive FIFO overflow overwrite enable */
+#define MCF_DSPI_DMCR_ROOE (0x01000000)
+/* Peripheral chip select strobe enable */
+#define MCF_DSPI_DMCR_PCSSE (0x02000000)
+/* Modified timing format enable */
+#define MCF_DSPI_DMCR_MTFE (0x04000000)
+/* Freeze */
+#define MCF_DSPI_DMCR_FRZ (0x08000000)
+/* DSPI configuration */
+#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
+/* Continuous SCK enable */
+#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000)
+/* Master/Slave mode select */
+#define MCF_DSPI_DMCR_MSTR (0x80000000)
+#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
+#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
+#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
+#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
+#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
+#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
+#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
+#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
+#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
+
+/* Bit definitions and macros for DTCR */
+/* SPI transfer count */
+#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
+
+/* Bit definitions and macros for DCTAR group */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR_DBR (0x80000000)
+#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
+#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
+#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
+#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
+#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
+#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
+#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
+#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
+#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
+#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
+#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
+#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
+#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
+#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
+#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
+
+/* Bit definitions and macros for DCTAR0 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR0_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR0_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR0_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR0_DBR (0x80000000)
+#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
+#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
+#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
+#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
+#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
+#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
+#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
+#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
+#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
+#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
+#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
+#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
+#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
+#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
+#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
+#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
+#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
+#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
+
+/* Bit definitions and macros for DCTAR1 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR1_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR1_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR1_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR1_DBR (0x80000000)
+
+
+/* Bit definitions and macros for DCTAR2 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR2_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR2_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR2_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR2_DBR (0x80000000)
+
+/* Bit definitions and macros for DCTAR3 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR3_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR3_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR3_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR3_DBR (0x80000000)
+
+/* Bit definitions and macros for DCTAR4 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR4_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR4_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR4_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR4_DBR (0x80000000)
+
+/* Bit definitions and macros for DCTAR5 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR5_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR5_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR5_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR5_DBR (0x80000000)
+
+/* Bit definitions and macros for DCTAR6 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR6_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR6_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR6_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR6_DBR (0x80000000)
+
+/* Bit definitions and macros for DCTAR7 */
+/* Baud rate scaler */
+#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F))
+/* Delay after transfer scaler */
+#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4)
+/* After SCK delay scaler */
+#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8)
+/* PCS to SCK delay scaler */
+#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12)
+/* Baud rate prescaler */
+#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16)
+/* Delay after transfer prescaler */
+#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18)
+/* After SCK delay prescaler */
+#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20)
+/* PCS to SCK delay prescaler */
+#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22)
+/* LSB first enable */
+#define MCF_DSPI_DCTAR7_LSBFE (0x01000000)
+/* Clock phase */
+#define MCF_DSPI_DCTAR7_CPHA (0x02000000)
+/* Clock polarity */
+#define MCF_DSPI_DCTAR7_CPOL (0x04000000)
+/* Frame size */
+#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27)
+/* Double baud rate */
+#define MCF_DSPI_DCTAR7_DBR (0x80000000)
+
+/* Bit definitions and macros for DSR */
+/* Receive next pointer */
+#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
+/* Receive FIFO counter */
+#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
+/* Transmit next pointer */
+#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
+/* Transmit FIFO counter */
+#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
+/* Receive FIFO drain flag */
+#define MCF_DSPI_DSR_RFDF (0x00020000)
+/* Receive FIFO overflow flag */
+#define MCF_DSPI_DSR_RFOF (0x00080000)
+/* Transmit FIFO fill flag */
+#define MCF_DSPI_DSR_TFFF (0x02000000)
+/* Transmit FIFO underflow flag */
+#define MCF_DSPI_DSR_TFUF (0x08000000)
+/* End of queue flag */
+#define MCF_DSPI_DSR_EOQF (0x10000000)
+/* Tx and Rx status (enabled | disabled) */
+#define MCF_DSPI_DSR_TXRXS (0x40000000)
+/* Transfer complete flag */
+#define MCF_DSPI_DSR_TCF (0x80000000)
+
+/* Bit definitions and macros for DRSER */
+/* Receive FIFO drain DMA or interrupt select */
+#define MCF_DSPI_DRSER_RFDFS (0x00010000)
+/* Receive FIFO drain request enable */
+#define MCF_DSPI_DRSER_RFDFE (0x00020000)
+/* Receive FIFO overflow request enable */
+#define MCF_DSPI_DRSER_RFOFE (0x00080000)
+/* Transmit FIFO fill DMA or interrupt select */
+#define MCF_DSPI_DRSER_TFFFS (0x01000000)
+/* Transmit FIFO fill request enable */
+#define MCF_DSPI_DRSER_TFFFE (0x02000000)
+/* Transmit FIFO underflow request enable */
+#define MCF_DSPI_DRSER_TFUFE (0x08000000)
+/* DSPI finished request enable */
+#define MCF_DSPI_DRSER_EOQFE (0x10000000)
+/* Transmission complete request enable */
+#define MCF_DSPI_DRSER_TCFE (0x80000000)
+
+/* Bit definitions and macros for DTFR */
+/* Transmit data */
+#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFR_PCS0 (0x00010000)
+/* Peripheral chip select 1 */
+#define MCF_DSPI_DTFR_PCS1 (0x00020000)
+/* Peripheral chip select 2 */
+#define MCF_DSPI_DTFR_PCS2 (0x00040000)
+/* Peripheral chip select 3 */
+#define MCF_DSPI_DTFR_PCS3 (0x00080000)
+/* Peripheral chip select 4 */
+#define MCF_DSPI_DTFR_PCS4 (0x00100000)
+/* Peripheral chip select 5 */
+#define MCF_DSPI_DTFR_PCS5 (0x00200000)
+/* Peripheral chip select 6 */
+#define MCF_DSPI_DTFR_PCS6 (0x00400000)
+/* Peripheral chip select 7 */
+#define MCF_DSPI_DTFR_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFR_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFR_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFR_CONT (0x80000000)
+
+/* Bit definitions and macros for DRFR */
+/* Receive data */
+#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DTFDR group */
+/* Transmit data */
+#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS0 (0x00010000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS1 (0x00020000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS2 (0x00040000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS3 (0x00080000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS4 (0x00100000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS5 (0x00200000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS6 (0x00400000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFDR_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFDR_CONT (0x80000000)
+
+/* Bit definitions and macros for DTFDR0 */
+/* Transmit data */
+#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS0 (0x00010000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS1 (0x00020000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS2 (0x00040000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS3 (0x00080000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS4 (0x00100000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS5 (0x00200000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS6 (0x00400000)
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR0_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR0_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFDR0_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFDR0_CONT (0x80000000)
+/* Bit definitions and macros for DTFDR1 */
+/* Transmit data */
+#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR1_PCS0 (0x00010000)
+/* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR1_PCS1 (0x00020000)
+/* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR1_PCS2 (0x00040000)
+/* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR1_PCS3 (0x00080000)
+/* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR1_PCS4 (0x00100000)
+/* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR1_PCS5 (0x00200000)
+/* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR1_PCS6 (0x00400000)
+/* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR1_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR1_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFDR1_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFDR1_CONT (0x80000000)
+
+/* Bit definitions and macros for DTFDR2 */
+#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR2_PCS0 (0x00010000)
+/* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR2_PCS1 (0x00020000)
+/* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR2_PCS2 (0x00040000)
+/* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR2_PCS3 (0x00080000)
+/* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR2_PCS4 (0x00100000)
+/* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR2_PCS5 (0x00200000)
+/* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR2_PCS6 (0x00400000)
+/* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR2_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR2_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFDR2_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFDR2_CONT (0x80000000)
+
+/* Bit definitions and macros for DTFDR3 */
+/* Transmit data */
+#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF))
+/* Peripheral chip select 0 */
+#define MCF_DSPI_DTFDR3_PCS0 (0x00010000)
+/* Peripheral chip select 1 */
+#define MCF_DSPI_DTFDR3_PCS1 (0x00020000)
+/* Peripheral chip select 2 */
+#define MCF_DSPI_DTFDR3_PCS2 (0x00040000)
+/* Peripheral chip select 3 */
+#define MCF_DSPI_DTFDR3_PCS3 (0x00080000)
+/* Peripheral chip select 4 */
+#define MCF_DSPI_DTFDR3_PCS4 (0x00100000)
+/* Peripheral chip select 5 */
+#define MCF_DSPI_DTFDR3_PCS5 (0x00200000)
+/* Peripheral chip select 6 */
+#define MCF_DSPI_DTFDR3_PCS6 (0x00400000)
+/* Peripheral chip select 7 */
+#define MCF_DSPI_DTFDR3_PCS7 (0x00800000)
+/* Clear SPI transfer counter */
+#define MCF_DSPI_DTFDR3_CTCNT (0x04000000)
+/* End of queue */
+#define MCF_DSPI_DTFDR3_EOQ (0x08000000)
+/* Clock and transfer attributes select */
+#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28)
+/* Continuous peripheral chip-select enable */
+#define MCF_DSPI_DTFDR3_CONT (0x80000000)
+
+/* Bit definitions and macros for DRFDR group */
+#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DRFDR0 */
+#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DRFDR1 */
+#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DRFDR2 */
+#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF))
+
+/* Bit definitions and macros for DRFDR3 */
+#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF))
+
+/********************************************************************/
+
+#endif /* __MCF5441X_DSPI_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_dtim.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_DTIM_H__
+#define __MCF5441X_DTIM_H__
+
+/*********************************************************************
+*
+* DMA Timers (DTIM)
+*
+*********************************************************************/
+/* Register read/write macros */
+#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
+#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
+#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
+#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
+#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
+#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
+#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
+#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
+#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
+#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
+#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
+#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
+#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
+#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
+#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
+#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
+#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
+#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
+#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
+#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
+#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
+#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
+#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
+#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
+
+/* Parameterized register read/write macros for multiple modules */
+/* DMA Timer Mode Register */
+#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000))
+/* DMA Timer Extended Mode Register */
+#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000))
+/* DMA Timer Event Register */
+#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000))
+/* DMA Timer Reference Register */
+#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000))
+/* DMA Timer Capture Register */
+#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000))
+/* DMA Timer Counter Register */
+#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000))
+
+/* Bit definitions and macros for DTMR */
+#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
+#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
+#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
+/* Output reference request/interrupt enable */
+#define MCF_DTIM_DTMR_ORRI (0x0010)
+#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
+#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
+#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
+#define MCF_DTIM_DTMR_RST_EN (0x0001)
+#define MCF_DTIM_DTMR_RST_RST (0x0000)
+#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
+#define MCF_DTIM_DTMR_CE_FALL (0x0080)
+#define MCF_DTIM_DTMR_CE_RISE (0x0040)
+#define MCF_DTIM_DTMR_CE_NONE (0x0000)
+#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
+#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
+#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
+#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
+
+/* Bit definitions and macros for DTXMR */
+#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
+#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
+#define MCF_DTIM_DTXMR_1588EN (0x20) /* Enable 1588 mode*/
+
+/* Bit definitions and macros for DTER */
+#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
+#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
+
+/* Interrupts used for system timers */
+#define MCFSIM_ICR_TIMER0 (0xFC048040+32)
+#define MCFSIM_ICR_TIMER1 (0xFC048040+33)
+#define MCFSIM_ICR_TIMER2 (0xFC048040+34)
+#define MCFSIM_ICR_TIMER3 (0xFC048040+35)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_DTIM_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_edma.h
@@ -0,0 +1,303 @@
+/* mcf5441x_edma.h
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Lanttor.Guo@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __MCF5441X_EDMA_H__
+#define __MCF5441X_EDMA_H__
+
+/*
+ * Enhanced DMA (EDMA)
+ */
+
+/* Channels */
+#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */
+#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */
+#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */
+#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */
+#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */
+#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */
+#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */
+#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */
+#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */
+#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */
+#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */
+#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */
+#define MCF_EDMA_CHAN_DSPI0_RX 12 /* DSPI0 Receive */
+#define MCF_EDMA_CHAN_DSPI0_TX 13 /* DSPI0 Transmit */
+#define MCF_EDMA_CHAN_DSPI1_RX 14 /* DSPI1 Receive */
+#define MCF_EDMA_CHAN_DSPI1_TX 15 /* DSPI1 Transmit */
+#define MCF_EDMA_CHAN_UART3_RX 16 /* UART3 Receive */
+#define MCF_EDMA_CHAN_UART3_TX 17 /* UART3 Transmit */
+#define MCF_EDMA_CHAN_UART4_RX 18 /* UART4 Receive */
+#define MCF_EDMA_CHAN_UART4_TX 19 /* UART4 Transmit */
+#define MCF_EDMA_CHAN_UART5_RX 20 /* UART5 Receive */
+#define MCF_EDMA_CHAN_UART5_TX 21 /* UART5 Transmit */
+#define MCF_EDMA_CHAN_UART6_RX 22 /* UART6 Receive */
+#define MCF_EDMA_CHAN_UART6_TX 23 /* UART6 Transmit */
+#define MCF_EDMA_CHAN_I2C0 24 /* I2C0 */
+#define MCF_EDMA_CHAN_I2C1 25 /* I2C1 */
+#define MCF_EDMA_CHAN_I2C2 26 /* I2C2 */
+#define MCF_EDMA_CHAN_I2C3 27 /* I2C3 */
+#define MCF_EDMA_CHAN_DSPI2_RX 28 /* DSPI2 Receive */
+#define MCF_EDMA_CHAN_DSPI2_TX 29 /* DSPI2 Transmit */
+#define MCF_EDMA_CHAN_N0 30 /* Available for software */
+#define MCF_EDMA_CHAN_N1 31 /* Available for software */
+#define MCF_EDMA_CHAN_UART7_RX 32 /* UART7 Receive */
+#define MCF_EDMA_CHAN_UART7_TX 33 /* UART7 Transmit */
+#define MCF_EDMA_CHAN_UART8_RX 34 /* UART8 Receive */
+#define MCF_EDMA_CHAN_UART8_TX 35 /* UART8 Transmit */
+#define MCF_EDMA_CHAN_UART9_RX 36 /* UART9 Receive */
+#define MCF_EDMA_CHAN_UART9_TX 37 /* UART9 Transmit */
+#define MCF_EDMA_CHAN_OW 38 /* 1-Wire */
+#define MCF_EDMA_CHAN_RESERVED 39 /* Reserved */
+#define MCF_EDMA_CHAN_I2C4 40 /* I2C4 */
+#define MCF_EDMA_CHAN_I2C5 41 /* I2C5 */
+#define MCF_EDMA_CHAN_N2 42 /* Available for software */
+#define MCF_EDMA_CHAN_N3 43 /* Available for software */
+#define MCF_EDMA_CHAN_DSPI3_RX 44 /* DSPI3 Receive */
+#define MCF_EDMA_CHAN_DSPI3_TX 45 /* DSPI3 Transmit */
+#define MCF_EDMA_CHAN_SSI0_RX0 48 /* SSI0 Receive 0 */
+#define MCF_EDMA_CHAN_SSI0_RX1 49 /* SSI0 Receive 1 */
+#define MCF_EDMA_CHAN_SSI0_TX0 50 /* SSI0 Transmit 0 */
+#define MCF_EDMA_CHAN_SSI0_TX1 51 /* SSI0 Transmit 1 */
+#define MCF_EDMA_CHAN_SSI1_RX0 52 /* SSI1 Receive 0 */
+#define MCF_EDMA_CHAN_SSI1_RX1 53 /* SSI1 Receive 1 */
+#define MCF_EDMA_CHAN_SSI1_TX0 54 /* SSI1 Transmit 0 */
+#define MCF_EDMA_CHAN_SSI1_TX1 55 /* SSI1 Transmit 1 */
+#define MCF_EDMA_CHAN_PWM_CAP 56 /* PWM Capture */
+#define MCF_EDMA_CHAN_PWM_VAL 57 /* PWM Value */
+#define MCF_EDMA_CHAN_RESERVED2 58 /* Reserved */
+#define MCF_EDMA_CHAN_ESDHC 59 /* eSDHC */
+#define MCF_EDMA_CHAN_ADC0 60 /* ADC 0 */
+#define MCF_EDMA_CHAN_ADC1 61 /* ADC 1 */
+#define MCF_EDMA_CHAN_DAC0 62 /* DAC 0 */
+#define MCF_EDMA_CHAN_DAC1 63 /* DAC 1 */
+
+/* Register read/write macros */
+#define MCF_EDMA_CR MCF_REG32(0xFC044000)
+#define MCF_EDMA_ES MCF_REG32(0xFC044004)
+#define MCF_EDMA_ERQH MCF_REG32(0xFC044008)
+#define MCF_EDMA_ERQL MCF_REG32(0xFC04400C)
+#define MCF_EDMA_EEIH MCF_REG32(0xFC044010)
+#define MCF_EDMA_EEIL MCF_REG32(0xFC044014)
+#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
+#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
+#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
+#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
+#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
+#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
+#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
+#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
+#define MCF_EDMA_INTH MCF_REG32(0xFC044020)
+#define MCF_EDMA_INTL MCF_REG32(0xFC044024)
+#define MCF_EDMA_ERRH MCF_REG32(0xFC044028)
+#define MCF_EDMA_ERRL MCF_REG32(0xFC04402C)
+#define MCF_EDMA_RSH MCF_REG32(0xFC044030)
+#define MCF_EDMA_RSL MCF_REG32(0xFC044034)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
+#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
+#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
+#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
+#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
+#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
+#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
+#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
+#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
+#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
+#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
+#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
+#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
+#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020))
+
+/* Bit definitions and macros for CR */
+#define MCF_EDMA_CR_EDBG (0x00000002)
+#define MCF_EDMA_CR_ERCA (0x00000004)
+#define MCF_EDMA_CR_ERGA (0x00000008)
+#define MCF_EDMA_CR_HOE (0x00000010)
+#define MCF_EDMA_CR_HALT (0x00000020)
+#define MCF_EDMA_CR_CLM (0x00000040)
+#define MCF_EDMA_CR_EMLM (0x00000080)
+#define MCF_EDMA_CR_GRP0PRI(x) (((x)&0x03)<<8)
+#define MCF_EDMA_CR_GRP1PRI(x) (((x)&0x03)<<10)
+#define MCF_EDMA_CR_GRP2PRI(x) (((x)&0x03)<<12)
+#define MCF_EDMA_CR_GRP3PRI(x) (((x)&0x03)<<14)
+#define MCF_EDMA_CR_ECX (0x00010000)
+#define MCF_EDMA_CR_CX (0x00020000)
+
+/* Bit definitions and macros for ES */
+#define MCF_EDMA_ES_DBE (0x00000001)
+#define MCF_EDMA_ES_SBE (0x00000002)
+#define MCF_EDMA_ES_SGE (0x00000004)
+#define MCF_EDMA_ES_NCE (0x00000008)
+#define MCF_EDMA_ES_DOE (0x00000010)
+#define MCF_EDMA_ES_DAE (0x00000020)
+#define MCF_EDMA_ES_SOE (0x00000040)
+#define MCF_EDMA_ES_SAE (0x00000080)
+#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000003F)<<8)
+#define MCF_EDMA_ES_CPE (0x00004000)
+#define MCF_EDMA_ES_GPE (0x00008000)
+#define MCF_EDMA_ES_ECX (0x00010000)
+#define MCF_EDMA_ES_VLD (0x80000000)
+
+/* Bit definitions and macros for ERQ: 0~63 bits */
+#define MCF_EDMA_ERQ_ERQH(x) (0x01<<x) /*32~63*/
+#define MCF_EDMA_ERQ_ERQL(x) (0x01<<x) /*0~31*/
+
+/* Bit definitions and macros for EEI: 0~63 bits */
+#define MCF_EDMA_EEI_EEIH(x) (0x01<<x) /*32~63*/
+#define MCF_EDMA_EEI_EEIL(x) (0x01<<x) /*0~31*/
+
+/* Bit definitions and macros for SERQ */
+#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x3F))
+#define MCF_EDMA_SERQ_SAER (0x40)
+#define MCF_EDMA_SERQ_NOP (0x80)
+
+/* Bit definitions and macros for CERQ */
+#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x3F))
+#define MCF_EDMA_CERQ_CAER (0x40)
+#define MCF_EDMA_CERQ_NOP (0x80)
+
+/* Bit definitions and macros for SEEI */
+#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x3F))
+#define MCF_EDMA_SEEI_SAEE (0x40)
+#define MCF_EDMA_SEEI_NOP (0x80)
+
+/* Bit definitions and macros for CEEI */
+#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x3F))
+#define MCF_EDMA_CEEI_CAEE (0x40)
+#define MCF_EDMA_CEEI_NOP (0x80)
+
+/* Bit definitions and macros for CINT */
+#define MCF_EDMA_CINT_CINT(x) (((x)&0x3F))
+#define MCF_EDMA_CINT_CAIR (0x40)
+#define MCF_EDMA_CINT_NOP (0x80)
+
+/* Bit definitions and macros for CERR */
+#define MCF_EDMA_CERR_CERR(x) (((x)&0x3F))
+#define MCF_EDMA_CERR_CAER (0x40)
+#define MCF_EDMA_CERR_NOP (0x80)
+
+/* Bit definitions and macros for SSRT */
+#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x3F))
+#define MCF_EDMA_SSRT_SAST (0x40)
+#define MCF_EDMA_SSRT_NOP (0x80)
+
+/* Bit definitions and macros for CDNE */
+#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x3F))
+#define MCF_EDMA_CDNE_CADN (0x40)
+#define MCF_EDMA_CDNE_NOP (0x80)
+
+/* Bit definitions and macros for INTR: 0~63 bits */
+#define MCF_EDMA_INTR_INTH(x) (0x01<<x) /*32~63*/
+#define MCF_EDMA_INTR_INTL(x) (0x01<<x) /*0~31*/
+
+/* Bit definitions and macros for ERR: 0~63 bits */
+#define MCF_EDMA_ERR_ERRH(x) (0x01<<x) /*32~63*/
+#define MCF_EDMA_ERR_ERRL(x) (0x01<<x) /*0~31*/
+
+/* Bit defineitions and macros for HRSH/HRSL */
+#define MCF_EDMA_HRS_HRSH(x) (0x01<<x) /*32~63*/
+#define MCF_EDMA_HRS_HRSL(x) (0x01<<x) /*0~31*/
+
+/* Bit definitions and macros for DCHPRI group */
+#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
+#define MCF_EDMA_DCHPRI_GRPPRI(x) (((x)&0x03) << 4)
+#define MCF_EDMA_DCHPRI_DPA (0x40)
+#define MCF_EDMA_DCHPRI_ECP (0x80)
+
+/* Bit definitions and macros for TCD_SADDR group */
+#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
+
+/* Bit definitions and macros for TCD_ATTR group */
+#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
+#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
+#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
+#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
+#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
+#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
+#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
+#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
+#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
+#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
+#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
+#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
+
+/* Bit definitions and macros for TCD_SOFF group */
+#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
+
+/* Bit definitions and macros for TCD_NBYTES group */
+#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
+#define MCF_EDMA_TCD_NBYTES_SMLOE (0x80000000)
+#define MCF_EDMA_TCD_NBYTES_DMLOE (0x40000000)
+#define MCF_EDMA_TCD_NBYTES_MLOFF(x) (((x)&0xFFFFF)<<20)
+#define MCF_EDMA_TCD_NBYTES_9BITS ((x)&0x1FF)
+
+/* Bit definitions and macros for TCD_SLAST group */
+#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
+
+/* Bit definitions and macros for TCD_DADDR group */
+#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
+
+/* Bit definitions and macros for TCD_CITER_ELINK group */
+#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
+#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
+
+/* Bit definitions and macros for TCD_CITER group */
+#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
+#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
+
+/* Bit definitions and macros for TCD_DOFF group */
+#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
+
+/* Bit definitions and macros for TCD_DLAST_SGA group */
+#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
+
+/* Bit definitions and macros for TCD_BITER_ELINK group */
+#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
+#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
+#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
+
+/* Bit definitions and macros for TCD_BITER group */
+#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
+#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
+
+/* Bit definitions and macros for TCD_CSR group */
+#define MCF_EDMA_TCD_CSR_START (0x0001)
+#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
+#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
+#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
+#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
+#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
+#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
+#define MCF_EDMA_TCD_CSR_DONE (0x0080)
+#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
+#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
+#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
+#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
+
+/* Bit definitions and macros for TCD0_CSR */
+#define MCF_EDMA_TCD0_CSR_START (0x0001)
+#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
+#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
+#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
+#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
+#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
+#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
+#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
+#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
+#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
+#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
+#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
+#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
+
+#endif /* __MCF5441X_EDMA_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_eport.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_EPORT_H__
+#define __MCF5441X_EPORT_H__
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR MCF_REG16(0xFC090000)
+#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
+#define MCF_EPORT_EPIER MCF_REG08(0xFC090003)
+#define MCF_EPORT_EPDR MCF_REG08(0xFC090004)
+#define MCF_EPORT_EPPDR MCF_REG08(0xFC090005)
+#define MCF_EPORT_EPFR MCF_REG08(0xFC090006)
+
+/* Bit definitions and macros for EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
+#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
+#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
+#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
+#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
+#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
+#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
+#define MCF_EPORT_EPPAR_LEVEL (0)
+#define MCF_EPORT_EPPAR_RISING (1)
+#define MCF_EPORT_EPPAR_FALLING (2)
+#define MCF_EPORT_EPPAR_BOTH (3)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
+#define MCF_EPORT_EPPAR_EPPA0_LEVEL (0x0000)
+#define MCF_EPORT_EPPAR_EPPA0_RISING (0x0001)
+#define MCF_EPORT_EPPAR_EPPA0_FALLING (0x0002)
+#define MCF_EPORT_EPPAR_EPPA0_BOTH (0x0003)
+
+/* Bit definitions and macros for EPIER */
+#define MCF_EPORT_EPIER_EPIE0 (0x01)
+#define MCF_EPORT_EPIER_EPIE1 (0x02)
+#define MCF_EPORT_EPIER_EPIE2 (0x04)
+#define MCF_EPORT_EPIER_EPIE3 (0x08)
+#define MCF_EPORT_EPIER_EPIE4 (0x10)
+#define MCF_EPORT_EPIER_EPIE5 (0x20)
+#define MCF_EPORT_EPIER_EPIE6 (0x40)
+#define MCF_EPORT_EPIER_EPIE7 (0x80)
+
+/* Bit definitions and macros for EPFR */
+#define MCF_EPORT_EPFR_EPF0 (0x01)
+#define MCF_EPORT_EPFR_EPF1 (0x02)
+#define MCF_EPORT_EPFR_EPF2 (0x04)
+#define MCF_EPORT_EPFR_EPF3 (0x08)
+#define MCF_EPORT_EPFR_EPF4 (0x10)
+#define MCF_EPORT_EPFR_EPF5 (0x20)
+#define MCF_EPORT_EPFR_EPF6 (0x40)
+#define MCF_EPORT_EPFR_EPF7 (0x80)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_EPORT_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_fbcs.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_FBCS_H__
+#define __MCF5441X_FBCS_H__
+
+/*********************************************************************
+*
+* FlexBus Chip Selects (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
+#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
+#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
+#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
+
+/* Parameterized register read/write macros for multiple registers */
+/* Chip-select Addr Register */
+#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
+/* Chip-select Mask Register */
+#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
+/* Chip-select Cntl Register */
+#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
+
+/* Bit definitions and macros for CSAR group */
+#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSAR0 */
+#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for CSMR group */
+#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
+#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
+#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
+#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
+#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
+#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
+#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
+#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
+#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
+#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
+#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
+#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
+#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
+#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
+#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
+#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for CSMR0 */
+#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
+#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
+#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
+#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
+#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
+#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
+#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
+#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
+#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
+#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
+#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
+#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
+#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
+#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
+#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
+#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
+#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
+#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
+#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
+#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
+#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
+#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
+
+/* Bit definitions and macros for CSCR group */
+#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
+#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
+#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
+#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
+#define MCF_FBCS_CSCR_BLS (0x00000200) /* Byte-lane shift */
+#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+/* Write address hold or deselect */
+#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
+/* Read address hold or deselect */
+#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+/* Secondary wait state enable */
+#define MCF_FBCS_CSCR_SWSEN (0x00800000)
+/* Secondary wait states */
+#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
+#define MCF_FBCS_CSCR_PS_8 (0x00000040)
+#define MCF_FBCS_CSCR_PS_16 (0x00000080)
+#define MCF_FBCS_CSCR_PS_32 (0x00000000)
+
+/* Bit definitions and macros for CSCR0 */
+#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
+#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
+#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
+#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
+#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+/* Write address hold or deselect */
+#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16)
+/* Read address hold or deselect */
+#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+/* Secondary wait state enable */
+#define MCF_FBCS_CSCR0_SWSEN (0x00800000)
+/* Secondary wait states */
+#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26)
+#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
+#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
+#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
+
+/* Bit definitions and macros for CSMR1 */
+#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
+#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
+#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
+
+/* Bit definitions and macros for CSCR1 */
+#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
+#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
+#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
+#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
+#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+/* Write address hold or deselect */
+#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16)
+/* Read address hold or deselect */
+#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+/* Secondary wait state enable */
+#define MCF_FBCS_CSCR1_SWSEN (0x00800000)
+/* Secondary wait states */
+#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for CSMR2 */
+#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
+#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
+#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
+
+/* Bit definitions and macros for CSCR2 */
+#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
+#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
+#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
+#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
+#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+/* Write address hold or deselect */
+#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16)
+/* Read address hold or deselect */
+#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+/* Secondary wait state enable */
+#define MCF_FBCS_CSCR2_SWSEN (0x00800000)
+/* Secondary wait states */
+#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26)
+
+/* Bit definitions and macros for CSMR3 */
+#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
+#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
+#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
+
+/* Bit definitions and macros for CSCR3 */
+#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
+#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
+#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
+#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
+#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
+#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
+/* Write address hold or deselect */
+#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16)
+/* Read address hold or deselect */
+#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18)
+#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
+/* Secondary wait state enable */
+#define MCF_FBCS_CSCR3_SWSEN (0x00800000)
+/* Secondary wait states */
+#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_FBCS_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_flexcan.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Lanttor Guo <b18203@freescale.com>
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef MCF5441X_FLEXCAN_H
+#define MCF5441X_FLEXCAN_H
+/*
+ * FlexCAN Module Configuration Register
+ */
+#define CANMCR_MDIS (0x80000000)
+#define CANMCR_FRZ (0x40000000)
+#define CANMCR_FEN (0x20000000)
+#define CANMCR_HALT (0x10000000)
+#define CANMCR_SOFTRST (0x02000000)
+#define CANMCR_NOTRDY (0x08000000)
+#define CANMCR_FRZACK (0x01000000)
+#define CANMCR_SUPV (0x00800000)
+#define CANMCR_WARN_EN (0x00200000)
+#define CANMCR_LPMACK (0x00100000)
+#define CANMCR_DOZE (0x00040000)
+#define CANMCR_SRXDIS (0x00020000)
+#define CANMCR_BCC (0x00010000)
+#define CANMCR_LPRIO_EN (0x00002000)
+#define CANMCR_AEN (0x00001000)
+#define CANMCR_IDAM_VAL(x) ((x & 0x3) << 8)
+#define CANMCR_MAXMB (0x0F)
+/*
+ * FlexCAN Control Register
+ */
+#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
+#define CANCTRL_RJW(x) (((x)&0x03)<<22)
+#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
+#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
+#define CANCTRL_BOFFMSK (0x00008000)
+#define CANCTRL_ERRMSK (0x00004000)
+#define CANCTRL_CLKSRC (0x00002000)
+#define CANCTRL_LPB (0x00001000)
+#define CANCTRL_TWRN_MSK (0x00000800)
+#define CANCTRL_RWRN_MSK (0x00000400)
+#define CANCTRL_SAMP(x) (((x)&0x01)<<7)
+#define CANCTRL_BOFFREC (0x00000040)
+#define CANCTRL_TSYNC (0x00000020)
+#define CANCTRL_LBUF (0x00000010)
+#define CANCTRL_LOM (0x00000008)
+#define CANCTRL_PROPSEG(x) ((x)&0x07)
+
+/*
+ * FlexCAN Error Counter Register
+ */
+#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
+#define ERRCNT_TXECTR(x) ((x)&0xFF)
+
+/*
+ * FlexCAN Error and Status Register
+ */
+#define ERRSTAT_TWRN_INT (0x00020000)
+#define ERRSTAT_RWRN_INT (0x00010000)
+#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
+#define ERRSTAT_ACKERR (0x00002000)
+#define ERRSTAT_CRCERR (0x00001000)
+#define ERRSTAT_FRMERR (0x00000800)
+#define ERRSTAT_STFERR (0x00000400)
+#define ERRSTAT_TXWRN (0x00000200)
+#define ERRSTAT_RXWRN (0x00000100)
+#define ERRSTAT_IDLE (0x00000080)
+#define ERRSTAT_TXRX (0x00000040)
+#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
+#define ERRSTAT_BOFFINT (0x00000004)
+#define ERRSTAT_ERRINT (0x00000002)
+
+/*
+ * Interrupt Mask Register
+ */
+#define IMASK_BUF15M (0x8000)
+#define IMASK_BUF14M (0x4000)
+#define IMASK_BUF13M (0x2000)
+#define IMASK_BUF12M (0x1000)
+#define IMASK_BUF11M (0x0800)
+#define IMASK_BUF10M (0x0400)
+#define IMASK_BUF9M (0x0200)
+#define IMASK_BUF8M (0x0100)
+#define IMASK_BUF7M (0x0080)
+#define IMASK_BUF6M (0x0040)
+#define IMASK_BUF5M (0x0020)
+#define IMASK_BUF4M (0x0010)
+#define IMASK_BUF3M (0x0008)
+#define IMASK_BUF2M (0x0004)
+#define IMASK_BUF1M (0x0002)
+#define IMASK_BUF0M (0x0001)
+#define IMASK_BUFnM(x) (0x1<<(x))
+#define IMASK_BUFF_ENABLE_ALL (0xFFFF)
+#define IMASK_BUFF_DISABLE_ALL (0x0000)
+
+/*
+ * Interrupt Flag Register
+ */
+#define IFLAG_BUF15M (0x8000)
+#define IFLAG_BUF14M (0x4000)
+#define IFLAG_BUF13M (0x2000)
+#define IFLAG_BUF12M (0x1000)
+#define IFLAG_BUF11M (0x0800)
+#define IFLAG_BUF10M (0x0400)
+#define IFLAG_BUF9M (0x0200)
+#define IFLAG_BUF8M (0x0100)
+#define IFLAG_BUF7M (0x0080)
+#define IFLAG_BUF6M (0x0040)
+#define IFLAG_BUF5M (0x0020)
+#define IFLAG_BUF4M (0x0010)
+#define IFLAG_BUF3M (0x0008)
+#define IFLAG_BUF2M (0x0004)
+#define IFLAG_BUF1M (0x0002)
+#define IFLAG_BUF0M (0x0001)
+#define IFLAG_BUFF_SET_ALL (0xFFFF)
+#define IFLAG_BUFF_CLEAR_ALL (0x0000)
+#define IFLAG_BUFnM(x) (0x1<<(x))
+
+/*
+ * Message Buffers
+ */
+#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
+#define MB_CNT_SRR (0x00400000)
+#define MB_CNT_IDE (0x00200000)
+#define MB_CNT_RTR (0x00100000)
+#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
+#define MB_PRIO(x) (((x)&0x7)<<29)
+#define MB_ID_STD (0x07FF)
+#define MB_ID_EXT (0x1FFFFFFF)
+#define MB_CODE_MASK (0xF0FFFFFF)
+#define CAN_MB 16
+#define PDEV_MAX 2
+
+#endif
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_gpio.h
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_GPIO_H__
+#define __MCF5441X_GPIO_H__
+
+/*********************************************************************
+*
+* General Purpose I/O Module (GPIO)
+*
+*********************************************************************/
+
+#define MCF_GPIO_PODR_A MCF_REG08(0xEC094000)
+#define MCF_GPIO_PODR_B MCF_REG08(0xEC094001)
+#define MCF_GPIO_PODR_C MCF_REG08(0xEC094002)
+#define MCF_GPIO_PODR_D MCF_REG08(0xEC094003)
+#define MCF_GPIO_PODR_E MCF_REG08(0xEC094004)
+#define MCF_GPIO_PODR_F MCF_REG08(0xEC094005)
+#define MCF_GPIO_PODR_G MCF_REG08(0xEC094006)
+#define MCF_GPIO_PODR_H MCF_REG08(0xEC094007)
+#define MCF_GPIO_PODR_I MCF_REG08(0xEC094008)
+#define MCF_GPIO_PODR_J MCF_REG08(0xEC094009)
+#define MCF_GPIO_PODR_K MCF_REG08(0xEC09400A)
+
+#define MCF_GPIO_PDDR_A MCF_REG08(0xEC09400C)
+#define MCF_GPIO_PDDR_B MCF_REG08(0xEC09400D)
+#define MCF_GPIO_PDDR_C MCF_REG08(0xEC09400E)
+#define MCF_GPIO_PDDR_D MCF_REG08(0xEC09400F)
+#define MCF_GPIO_PDDR_E MCF_REG08(0xEC094010)
+#define MCF_GPIO_PDDR_F MCF_REG08(0xEC094011)
+#define MCF_GPIO_PDDR_G MCF_REG08(0xEC094012)
+#define MCF_GPIO_PDDR_H MCF_REG08(0xEC094013)
+#define MCF_GPIO_PDDR_I MCF_REG08(0xEC094014)
+#define MCF_GPIO_PDDR_J MCF_REG08(0xEC094015)
+#define MCF_GPIO_PDDR_K MCF_REG08(0xEC094016)
+
+#define MCF_GPIO_PPDSDR_A MCF_REG08(0xEC094018)
+#define MCF_GPIO_PPDSDR_B MCF_REG08(0xEC094019)
+#define MCF_GPIO_PPDSDR_C MCF_REG08(0xEC09401A)
+#define MCF_GPIO_PPDSDR_D MCF_REG08(0xEC09401B)
+#define MCF_GPIO_PPDSDR_E MCF_REG08(0xEC09401C)
+#define MCF_GPIO_PPDSDR_F MCF_REG08(0xEC09401D)
+#define MCF_GPIO_PPDSDR_G MCF_REG08(0xEC09401E)
+#define MCF_GPIO_PPDSDR_H MCF_REG08(0xEC09401F)
+#define MCF_GPIO_PPDSDR_I MCF_REG08(0xEC094020)
+#define MCF_GPIO_PPDSDR_J MCF_REG08(0xEC094021)
+#define MCF_GPIO_PPDSDR_K MCF_REG08(0xEC094022)
+
+#define MCF_GPIO_PCLRR_A MCF_REG08(0xEC094024)
+#define MCF_GPIO_PCLRR_B MCF_REG08(0xEC094025)
+#define MCF_GPIO_PCLRR_C MCF_REG08(0xEC094026)
+#define MCF_GPIO_PCLRR_D MCF_REG08(0xEC094027)
+#define MCF_GPIO_PCLRR_E MCF_REG08(0xEC094028)
+#define MCF_GPIO_PCLRR_F MCF_REG08(0xEC094029)
+#define MCF_GPIO_PCLRR_G MCF_REG08(0xEC09402A)
+#define MCF_GPIO_PCLRR_H MCF_REG08(0xEC09402B)
+#define MCF_GPIO_PCLRR_I MCF_REG08(0xEC09402C)
+#define MCF_GPIO_PCLRR_J MCF_REG08(0xEC09402D)
+#define MCF_GPIO_PCLRR_K MCF_REG08(0xEC09402E)
+
+#define MCF_GPIO_PCR_A MCF_REG16(0xEC094030)
+#define MCF_GPIO_PCR_B MCF_REG16(0xEC094032)
+#define MCF_GPIO_PCR_C MCF_REG16(0xEC094034)
+#define MCF_GPIO_PCR_D MCF_REG16(0xEC094036)
+#define MCF_GPIO_PCR_E MCF_REG16(0xEC094038)
+#define MCF_GPIO_PCR_F MCF_REG16(0xEC09403A)
+#define MCF_GPIO_PCR_G MCF_REG16(0xEC09403C)
+
+#define MCF_GPIO_PCR_H MCF_REG16(0xEC09403E)
+#define MCF_GPIO_PCR_I MCF_REG16(0xEC094040)
+#define MCF_GPIO_PCR_J MCF_REG16(0xEC094042)
+#define MCF_GPIO_PCR_K MCF_REG16(0xEC094044)
+
+#define MCF_GPIO_PODR_G4_VAL (0x01 << 4)
+#define MCF_GPIO_PODR_G4_MASK (0xff & ~MCF_GPIO_PODR_G4_VAL)
+#define MCF_GPIO_PDDR_G4_OUTPUT (0x01 << 4)
+#define MCF_GPIO_PDDR_G4_MASK (0xff & ~MCF_GPIO_PDDR_G4_OUTPUT)
+
+#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xEC094048)
+#define MCF_GPIO_PAR_BE MCF_REG08(0xEC094049)
+#define MCF_GPIO_PAR_CS MCF_REG08(0xEC09404A)
+#define MCF_GPIO_PAR_CANI2C MCF_REG08(0xEC09404B)
+#define MCF_GPIO_PAR_IRQ0H MCF_REG08(0xEC09404C)
+#define MCF_GPIO_PAR_IRQ0L MCF_REG08(0xEC09404D)
+#define MCF_GPIO_PAR_DSPI0WH MCF_REG08(0xEC09404E)
+#define MCF_GPIO_PAR_DSPI0WL MCF_REG08(0xEC09404F)
+#define MCF_GPIO_PAR_TIMER MCF_REG08(0xEC094050)
+#define MCF_GPIO_PAR_UART2 MCF_REG08(0xEC094051)
+#define MCF_GPIO_PAR_UART1 MCF_REG08(0xEC094052)
+#define MCF_GPIO_PAR_UART0 MCF_REG08(0xEC094053)
+#define MCF_GPIO_PAR_ESDHCH MCF_REG08(0xEC094054)
+#define MCF_GPIO_PAR_ESDHCL MCF_REG08(0xEC094055)
+#define MCF_GPIO_PAR_SIMP0H MCF_REG08(0xEC094056)
+#define MCF_GPIO_PAR_SIMP0L MCF_REG08(0xEC094057)
+#define MCF_GPIO_PAR_SSI0H MCF_REG08(0xEC094058)
+#define MCF_GPIO_PAR_SSI0L MCF_REG08(0xEC094059)
+#define MCF_GPIO_PAR_DBGH1 MCF_REG08(0xEC09405A)
+#define MCF_GPIO_PAR_DBGH0 MCF_REG08(0xEC09405B)
+#define MCF_GPIO_PAR_DBGL MCF_REG08(0xEC09405C)
+#define MCF_GPIO_PAR_FEC MCF_REG08(0xEC09405E)
+#define MCF_GPIO_MSCR_SDRAMC MCF_REG08(0xEC094064)
+#define MCF_GPIO_SRCR_FB1 MCF_REG08(0xEC094064)
+#define MCF_GPIO_SRCR_FB2 MCF_REG08(0xEC094065)
+#define MCF_GPIO_SRCR_FB3 MCF_REG08(0xEC094066)
+#define MCF_GPIO_SRCR_FB4 MCF_REG08(0xEC094067)
+#define MCF_GPIO_SRCR_DSPI0W MCF_REG08(0xEC094068)
+#define MCF_GPIO_SRCR_CANI2C MCF_REG08(0xEC094069)
+#define MCF_GPIO_SRCR_IRQ0 MCF_REG08(0xEC09406A)
+#define MCF_GPIO_SRCR_TIMER MCF_REG08(0xEC09406B)
+#define MCF_GPIO_SRCR_UART MCF_REG08(0xEC09406C)
+#define MCF_GPIO_SRCR_FEC MCF_REG08(0xEC09406D)
+#define MCF_GPIO_SRCR_SDHC MCF_REG08(0xEC09406E)
+#define MCF_GPIO_SRCR_SIM0 MCF_REG08(0xEC09406F)
+#define MCF_GPIO_SRCR_SSI0 MCF_REG08(0xEC094070)
+
+#define MCF_GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
+#define MCF_GPIO_PAR_FBCTL_ALE_MASK (0x3F)
+#define MCF_GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
+#define MCF_GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
+#define MCF_GPIO_PAR_FBCTL_ALE_GPIO (0x00)
+#define MCF_GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
+#define MCF_GPIO_PAR_FBCTL_OE_MASK (0xCF)
+#define MCF_GPIO_PAR_FBCTL_OE_FB_OE (0x30)
+#define MCF_GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
+#define MCF_GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
+#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define MCF_GPIO_PAR_FBCTL_FBCLK (0x08)
+#define MCF_GPIO_PAR_FBCTL_RW (0x04)
+#define MCF_GPIO_PAR_FBCTL_TA(x) ((x)&3)
+#define MCF_GPIO_PAR_FBCTL_TA_MASK (0xFC)
+#define MCF_GPIO_PAR_FBCTL_TA_TA (0x03)
+#define MCF_GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
+#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
+
+#define MCF_GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
+#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define MCF_GPIO_PAR_BE_BE3_CS3 (0x80)
+#define MCF_GPIO_PAR_BE_BE3_FB_A1 (0x40)
+#define MCF_GPIO_PAR_BE_BE3_NFC_ALE (0x40)
+#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
+#define MCF_GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
+#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
+#define MCF_GPIO_PAR_BE_BE2_CS2 (0x20)
+#define MCF_GPIO_PAR_BE_BE2_FB_A0 (0x10)
+#define MCF_GPIO_PAR_BE_BE2_NFC_CLE (0x10)
+#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
+#define MCF_GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_BE_BE1_MASK (0xF3)
+#define MCF_GPIO_PAR_BE_BE1_BE1 (0x0C)
+#define MCF_GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
+#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
+#define MCF_GPIO_PAR_BE_BS0(x) ((x)&0x03)
+#define MCF_GPIO_PAR_BE_BE0_MASK (0xFC)
+#define MCF_GPIO_PAR_BE_BE0_BE0 (0x03)
+#define MCF_GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
+#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
+
+#define MCF_GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_CS_CS5_MASK (0x3F)
+#define MCF_GPIO_PAR_CS_CS5_CS5 (0xC0)
+#define MCF_GPIO_PAR_CS_CS5_DACK1 (0x80)
+#define MCF_GPIO_PAR_CS_CS5_GPIO (0x00)
+#define MCF_GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_CS_CS4_MASK (0xCF)
+#define MCF_GPIO_PAR_CS_CS4_CS4 (0x30)
+#define MCF_GPIO_PAR_CS_CS4_DREQ1 (0x20)
+#define MCF_GPIO_PAR_CS_CS4_GPIO (0x00)
+#define MCF_GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_CS_CS1_MASK (0xF3)
+#define MCF_GPIO_PAR_CS_CS1_CS1 (0x0C)
+#define MCF_GPIO_PAR_CS_CS1_NFC_CE (0x04)
+#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
+#define MCF_GPIO_PAR_CS_CS0_CS0 (0x01)
+
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
+#define MCF_GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
+#define MCF_GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
+#define MCF_GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
+#define MCF_GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
+
+#define MCF_GPIO_PAR_IRQH_IRQ7 (0x10)
+#define MCF_GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
+#define MCF_GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
+#define MCF_GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
+#define MCF_GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
+#define MCF_GPIO_PAR_IRQH_IRQ1 (0x01)
+
+#define MCF_GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
+#define MCF_GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
+#define MCF_GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
+#define MCF_GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
+#define MCF_GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
+#define MCF_GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
+#define MCF_GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
+#define MCF_GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
+#define MCF_GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
+#define MCF_GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
+#define MCF_GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
+#define MCF_GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
+#define MCF_GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
+#define MCF_GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
+
+#define MCF_GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_DSPI0_SIN_MASK (0x3F)
+#define MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
+#define MCF_GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
+#define MCF_GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
+#define MCF_GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
+#define MCF_GPIO_PAR_DSPI0_SIN_GPIO (0x00)
+#define MCF_GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
+#define MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
+#define MCF_GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
+#define MCF_GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
+#define MCF_GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
+#define MCF_GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
+#define MCF_GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_DSPI0_SCK_MASK (0xF3)
+#define MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
+#define MCF_GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
+#define MCF_GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
+#define MCF_GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
+#define MCF_GPIO_PAR_DSPI0_SCK_GPIO (0x00)
+#define MCF_GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
+#define MCF_GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
+#define MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
+#define MCF_GPIO_PAR_DSPI0_PCS0_SS (0x03)
+#define MCF_GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
+#define MCF_GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
+#define MCF_GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
+
+#define MCF_GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
+#define MCF_GPIO_PAR_DSPIOW_SBF_CS (0x80)
+#define MCF_GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
+#define MCF_GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
+#define MCF_GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
+#define MCF_GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
+
+#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define MCF_GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
+#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
+#define MCF_GPIO_PAR_TIMER_T3IN_ULPI_DIR (0x40)
+#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define MCF_GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
+#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define MCF_GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
+#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define MCF_GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
+#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define MCF_GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
+#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define MCF_GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
+#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define MCF_GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
+#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
+#define MCF_GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
+#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+#define MCF_GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_UART2_U2CTS_MASK (0x3F)
+#define MCF_GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
+#define MCF_GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
+#define MCF_GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
+#define MCF_GPIO_PAR_UART2_U2CTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_UART2_U2RTS_MASK (0xCF)
+#define MCF_GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
+#define MCF_GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
+#define MCF_GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
+#define MCF_GPIO_PAR_UART2_U2RTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_UART2_U2RXD_MASK (0xF3)
+#define MCF_GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
+#define MCF_GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
+#define MCF_GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
+#define MCF_GPIO_PAR_UART2_U2RXD_GPIO (0x00)
+#define MCF_GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
+#define MCF_GPIO_PAR_UART2_U2TXD_MASK (0xFC)
+#define MCF_GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
+#define MCF_GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
+#define MCF_GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
+#define MCF_GPIO_PAR_UART2_U2TXD_GPIO (0x00)
+
+#define MCF_GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_UART1_U1CTS_MASK (0x3F)
+#define MCF_GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
+#define MCF_GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
+#define MCF_GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
+#define MCF_GPIO_PAR_UART1_U1CTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_UART1_U1RTS_MASK (0xCF)
+#define MCF_GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
+#define MCF_GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
+#define MCF_GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
+#define MCF_GPIO_PAR_UART1_U1RTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_UART1_U1RXD_MASK (0xF3)
+#define MCF_GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
+#define MCF_GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
+#define MCF_GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
+#define MCF_GPIO_PAR_UART1_U1RXD_GPIO (0x00)
+#define MCF_GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
+#define MCF_GPIO_PAR_UART1_U1TXD_MASK (0xFC)
+#define MCF_GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
+#define MCF_GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
+#define MCF_GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
+#define MCF_GPIO_PAR_UART1_U1TXD_GPIO (0x00)
+
+#define MCF_GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_UART0_U0CTS_MASK (0x3F)
+#define MCF_GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
+#define MCF_GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
+#define MCF_GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
+#define MCF_GPIO_PAR_UART0_U0CTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_UART0_U0RTS_MASK (0xCF)
+#define MCF_GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
+#define MCF_GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
+#define MCF_GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
+#define MCF_GPIO_PAR_UART0_U0RTS_GPIO (0x00)
+#define MCF_GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_UART0_U0RXD_MASK (0xF3)
+#define MCF_GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
+#define MCF_GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
+#define MCF_GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
+#define MCF_GPIO_PAR_UART0_U0RXD_GPIO (0x00)
+#define MCF_GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
+#define MCF_GPIO_PAR_UART0_U0TXD_MASK (0xFC)
+#define MCF_GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
+#define MCF_GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
+#define MCF_GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
+#define MCF_GPIO_PAR_UART0_U0TXD_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
+#define MCF_GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
+#define MCF_GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
+#define MCF_GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
+#define MCF_GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
+#define MCF_GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
+#define MCF_GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
+#define MCF_GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
+#define MCF_GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
+#define MCF_GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
+#define MCF_GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
+#define MCF_GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
+#define MCF_GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
+#define MCF_GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
+#define MCF_GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
+#define MCF_GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
+#define MCF_GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
+#define MCF_GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
+#define MCF_GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
+#define MCF_GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_SDHCL_CMD_MASK (0xF3)
+#define MCF_GPIO_PAR_SDHCL_CMD_CMD (0x0C)
+#define MCF_GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
+#define MCF_GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
+#define MCF_GPIO_PAR_SDHCL_CMD_GPIO (0x00)
+#define MCF_GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SDHCL_CLK_MASK (0xFC)
+#define MCF_GPIO_PAR_SDHCL_CLK_CLK (0x03)
+#define MCF_GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
+#define MCF_GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
+#define MCF_GPIO_PAR_SDHCL_CLK_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
+#define MCF_GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
+#define MCF_GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
+#define MCF_GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
+#define MCF_GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
+#define MCF_GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
+#define MCF_GPIO_PAR_SIMP0H_VEN_VEN (0x30)
+#define MCF_GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
+#define MCF_GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
+#define MCF_GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_SIMP0H_RST_MASK (0xF3)
+#define MCF_GPIO_PAR_SIMP0H_RST_RST (0x0C)
+#define MCF_GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
+#define MCF_GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
+#define MCF_GPIO_PAR_SIMP0H_RST_GPIO (0x00)
+#define MCF_GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SIMP0H_PD_MASK (0xFC)
+#define MCF_GPIO_PAR_SIMP0H_PD_PD (0x03)
+#define MCF_GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
+#define MCF_GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
+#define MCF_GPIO_PAR_SIMP0H_PD_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
+#define MCF_GPIO_PAR_SIMP0L_CLK_CLK (0x03)
+#define MCF_GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
+#define MCF_GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
+#define MCF_GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
+#define MCF_GPIO_PAR_SSI0H_RXD_MASK (0x3F)
+#define MCF_GPIO_PAR_SSI0H_RXD_RXD (0xC0)
+#define MCF_GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
+#define MCF_GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
+#define MCF_GPIO_PAR_SSI0H_RXD_GPIO (0x00)
+#define MCF_GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
+#define MCF_GPIO_PAR_SSI0H_TXD_MASK (0xCF)
+#define MCF_GPIO_PAR_SSI0H_TXD_TXD (0x30)
+#define MCF_GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
+#define MCF_GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
+#define MCF_GPIO_PAR_SSI0H_TXD_GPIO (0x00)
+#define MCF_GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
+#define MCF_GPIO_PAR_SSI0H_FS_MASK (0xF3)
+#define MCF_GPIO_PAR_SSI0H_FS_FS (0x0C)
+#define MCF_GPIO_PAR_SSI0H_FS_U7TXD (0x08)
+#define MCF_GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
+#define MCF_GPIO_PAR_SSI0H_FS_GPIO (0x00)
+#define MCF_GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
+#define MCF_GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
+#define MCF_GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
+#define MCF_GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
+#define MCF_GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
+
+#define MCF_GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
+#define MCF_GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
+#define MCF_GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
+#define MCF_GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
+#define MCF_GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
+#define MCF_GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
+
+#define MCF_GPIO_PAR_DEBUGH1_DAT3 (0x40)
+#define MCF_GPIO_PAR_DEBUGH1_DAT2 (0x10)
+#define MCF_GPIO_PAR_DEBUGH1_DAT1 (0x04)
+#define MCF_GPIO_PAR_DEBUGH1_DAT0 (0x01)
+
+#define MCF_GPIO_PAR_DEBUGH0_PST3 (0x40)
+#define MCF_GPIO_PAR_DEBUGH0_PST2 (0x10)
+#define MCF_GPIO_PAR_DEBUGH0_PST1 (0x04)
+#define MCF_GPIO_PAR_DEBUGH0_PST0 (0x01)
+
+#define MCF_GPIO_PAR_DEBUGL_ALLPST (0x01)
+
+#define MCF_GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
+#define MCF_GPIO_PAR_FEC_FEC_MASK (0xF0)
+#define MCF_GPIO_PAR_FEC_FEC_GPIO (0x0D)
+#define MCF_GPIO_PAR_FEC_FEC_RMII1 (0x0C)
+#define MCF_GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
+#define MCF_GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0 (0x09)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define MCF_GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
+#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
+#define MCF_GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
+#define MCF_GPIO_PAR_FEC_FEC_MIIFUL (0x00)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_GPIO_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_intc.h
@@ -0,0 +1,727 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_INTC_H__
+#define __MCF5441X_INTC_H__
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
+#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
+#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
+#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
+#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
+#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
+#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
+#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
+#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
+#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
+#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
+#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
+#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
+#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
+#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
+#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
+#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
+#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
+#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
+#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
+#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
+#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
+#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
+#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
+#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
+#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
+#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
+#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
+#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
+#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
+#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
+#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
+#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
+#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
+#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
+#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
+#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
+#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
+#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
+#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
+#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
+#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
+#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
+#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
+#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
+#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
+#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
+#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
+#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
+#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
+#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
+#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
+#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
+#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
+#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
+#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
+#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
+#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
+#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
+#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
+#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
+#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
+#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
+#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
+#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
+#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
+#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
+#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
+#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
+#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
+#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
+#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
+#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
+#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
+#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
+#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
+#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
+#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
+#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
+#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
+#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
+#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
+#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
+#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
+#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
+#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
+#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
+#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
+#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
+#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
+#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
+#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
+#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
+#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
+#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
+#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
+#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
+#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
+#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
+#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
+#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
+#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
+#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
+#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
+#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
+#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
+#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
+#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
+#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
+#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
+#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
+#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
+#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
+#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
+#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
+#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
+#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
+#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
+#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
+#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
+#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
+#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
+#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
+#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
+#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
+#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
+#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
+#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
+#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
+#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
+#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
+#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
+#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
+#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
+#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
+#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
+#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
+#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
+#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
+#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
+#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
+#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
+#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
+#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
+#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
+#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
+#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
+#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
+#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
+#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
+#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
+#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
+#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
+#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
+#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
+#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
+#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
+#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
+#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
+#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
+#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
+#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
+#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
+#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
+
+#define MCF_INTC2_SIMR MCF_REG08(0xFC05001C)
+#define MCF_INTC2_CIMR MCF_REG08(0xFC05001D)
+#define MCF_INTC2_ICR31 MCF_REG08(0xFC05005F)
+
+/* Parameterized register read/write macros for multiple registers */
+#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
+#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
+#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
+#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
+#define MCF_INTC2_ICR(x) MCF_REG08(0xFC050041+((x-1)*0x001))
+
+/* Parameterized register read/write macros for multiple modules */
+#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
+#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
+#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
+#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
+#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
+#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
+#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
+#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
+#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
+#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
+#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
+#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
+#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
+#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
+#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
+#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
+#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
+#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
+#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
+#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
+#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
+#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
+#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
+#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
+#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
+#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
+#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
+#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
+#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
+#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
+#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
+#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
+#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
+#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
+#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
+#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
+#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
+#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
+#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
+#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
+#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
+#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
+#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
+#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
+#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
+#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
+#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
+#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
+#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
+#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
+#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
+#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
+#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
+#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
+#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
+#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
+#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
+#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
+#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
+#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
+#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
+#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
+#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
+#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
+#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
+#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
+#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
+#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
+#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
+#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
+#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
+#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
+#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
+#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
+#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
+#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
+#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
+#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
+#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
+#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
+#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
+#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
+
+/* Bit definitions and macros for IPRH */
+#define MCF_INTC_IPRH_INT32 (0x00000001)
+#define MCF_INTC_IPRH_INT33 (0x00000002)
+#define MCF_INTC_IPRH_INT34 (0x00000004)
+#define MCF_INTC_IPRH_INT35 (0x00000008)
+#define MCF_INTC_IPRH_INT36 (0x00000010)
+#define MCF_INTC_IPRH_INT37 (0x00000020)
+#define MCF_INTC_IPRH_INT38 (0x00000040)
+#define MCF_INTC_IPRH_INT39 (0x00000080)
+#define MCF_INTC_IPRH_INT40 (0x00000100)
+#define MCF_INTC_IPRH_INT41 (0x00000200)
+#define MCF_INTC_IPRH_INT42 (0x00000400)
+#define MCF_INTC_IPRH_INT43 (0x00000800)
+#define MCF_INTC_IPRH_INT44 (0x00001000)
+#define MCF_INTC_IPRH_INT45 (0x00002000)
+#define MCF_INTC_IPRH_INT46 (0x00004000)
+#define MCF_INTC_IPRH_INT47 (0x00008000)
+#define MCF_INTC_IPRH_INT48 (0x00010000)
+#define MCF_INTC_IPRH_INT49 (0x00020000)
+#define MCF_INTC_IPRH_INT50 (0x00040000)
+#define MCF_INTC_IPRH_INT51 (0x00080000)
+#define MCF_INTC_IPRH_INT52 (0x00100000)
+#define MCF_INTC_IPRH_INT53 (0x00200000)
+#define MCF_INTC_IPRH_INT54 (0x00400000)
+#define MCF_INTC_IPRH_INT55 (0x00800000)
+#define MCF_INTC_IPRH_INT56 (0x01000000)
+#define MCF_INTC_IPRH_INT57 (0x02000000)
+#define MCF_INTC_IPRH_INT58 (0x04000000)
+#define MCF_INTC_IPRH_INT59 (0x08000000)
+#define MCF_INTC_IPRH_INT60 (0x10000000)
+#define MCF_INTC_IPRH_INT61 (0x20000000)
+#define MCF_INTC_IPRH_INT62 (0x40000000)
+#define MCF_INTC_IPRH_INT63 (0x80000000)
+
+/* Bit definitions and macros for IPRL */
+#define MCF_INTC_IPRL_INT0 (0x00000001)
+#define MCF_INTC_IPRL_INT1 (0x00000002)
+#define MCF_INTC_IPRL_INT2 (0x00000004)
+#define MCF_INTC_IPRL_INT3 (0x00000008)
+#define MCF_INTC_IPRL_INT4 (0x00000010)
+#define MCF_INTC_IPRL_INT5 (0x00000020)
+#define MCF_INTC_IPRL_INT6 (0x00000040)
+#define MCF_INTC_IPRL_INT7 (0x00000080)
+#define MCF_INTC_IPRL_INT8 (0x00000100)
+#define MCF_INTC_IPRL_INT9 (0x00000200)
+#define MCF_INTC_IPRL_INT10 (0x00000400)
+#define MCF_INTC_IPRL_INT11 (0x00000800)
+#define MCF_INTC_IPRL_INT12 (0x00001000)
+#define MCF_INTC_IPRL_INT13 (0x00002000)
+#define MCF_INTC_IPRL_INT14 (0x00004000)
+#define MCF_INTC_IPRL_INT15 (0x00008000)
+#define MCF_INTC_IPRL_INT16 (0x00010000)
+#define MCF_INTC_IPRL_INT17 (0x00020000)
+#define MCF_INTC_IPRL_INT18 (0x00040000)
+#define MCF_INTC_IPRL_INT19 (0x00080000)
+#define MCF_INTC_IPRL_INT20 (0x00100000)
+#define MCF_INTC_IPRL_INT21 (0x00200000)
+#define MCF_INTC_IPRL_INT22 (0x00400000)
+#define MCF_INTC_IPRL_INT23 (0x00800000)
+#define MCF_INTC_IPRL_INT24 (0x01000000)
+#define MCF_INTC_IPRL_INT25 (0x02000000)
+#define MCF_INTC_IPRL_INT26 (0x04000000)
+#define MCF_INTC_IPRL_INT27 (0x08000000)
+#define MCF_INTC_IPRL_INT28 (0x10000000)
+#define MCF_INTC_IPRL_INT29 (0x20000000)
+#define MCF_INTC_IPRL_INT30 (0x40000000)
+#define MCF_INTC_IPRL_INT31 (0x80000000)
+
+/* Bit definitions and macros for IMRH */
+#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
+#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
+#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
+#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
+#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
+#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
+#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
+#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
+#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
+#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
+#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
+#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
+#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
+#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
+#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
+#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
+#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
+#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
+#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
+#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
+#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
+#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
+#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
+#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
+#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
+#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
+#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
+#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
+#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
+
+/* Bit definitions and macros for IMRL */
+#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
+#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
+#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
+#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
+#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
+#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
+#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
+#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
+#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
+#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
+#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
+#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
+#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
+#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
+#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
+#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
+#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
+#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
+#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
+#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
+#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
+#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
+#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
+#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
+#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
+#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
+#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
+#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
+#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
+
+/* Bit definitions and macros for INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
+#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
+#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
+#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
+#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
+#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
+#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
+#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
+#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
+#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
+#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
+#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
+#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
+#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
+#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
+#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
+#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
+#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
+#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
+#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
+#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
+#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
+#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
+#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
+#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
+#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
+#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
+#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
+#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
+
+/* Bit definitions and macros for INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
+#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
+#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
+#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
+#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
+#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
+#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
+#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
+#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
+#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
+#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
+#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
+#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
+#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
+#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
+#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
+#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
+#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
+#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
+#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
+#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
+#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
+#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
+#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
+#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
+#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
+#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
+#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
+#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
+
+/* Bit definitions and macros for ICONFIG */
+#define MCF_INTC_ICONFIG_EMASK (0x0020)
+#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
+#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
+#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
+#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
+#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
+#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
+#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
+
+/* Bit definitions and macros for SIMR */
+#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CIMR */
+#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
+
+/* Bit definitions and macros for CLMASK */
+#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for SLMASK */
+#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
+
+/* Bit definitions and macros for ICR group */
+#define MCF_INTC_ICR_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR1 */
+#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR2 */
+#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR3 */
+#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR4 */
+#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR5 */
+#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR6 */
+#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR7 */
+#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR8 */
+#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR9 */
+#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR10 */
+#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR11 */
+#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR12 */
+#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR13 */
+#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR14 */
+#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR15 */
+#define MCF_INTC_ICR15_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR16 */
+#define MCF_INTC_ICR16_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR17 */
+#define MCF_INTC_ICR17_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR18 */
+#define MCF_INTC_ICR18_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR19 */
+#define MCF_INTC_ICR19_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR20 */
+#define MCF_INTC_ICR20_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR21 */
+#define MCF_INTC_ICR21_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR22 */
+#define MCF_INTC_ICR22_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR23 */
+#define MCF_INTC_ICR23_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR24 */
+#define MCF_INTC_ICR24_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR25 */
+#define MCF_INTC_ICR25_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR26 */
+#define MCF_INTC_ICR26_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR27 */
+#define MCF_INTC_ICR27_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR28 */
+#define MCF_INTC_ICR28_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR29 */
+#define MCF_INTC_ICR29_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR30 */
+#define MCF_INTC_ICR30_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR31 */
+#define MCF_INTC_ICR31_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR32 */
+#define MCF_INTC_ICR32_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR33 */
+#define MCF_INTC_ICR33_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR34 */
+#define MCF_INTC_ICR34_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR35 */
+#define MCF_INTC_ICR35_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR36 */
+#define MCF_INTC_ICR36_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR37 */
+#define MCF_INTC_ICR37_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR38 */
+#define MCF_INTC_ICR38_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR39 */
+#define MCF_INTC_ICR39_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR40 */
+#define MCF_INTC_ICR40_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR41 */
+#define MCF_INTC_ICR41_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR42 */
+#define MCF_INTC_ICR42_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR43 */
+#define MCF_INTC_ICR43_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR44 */
+#define MCF_INTC_ICR44_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR45 */
+#define MCF_INTC_ICR45_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR46 */
+#define MCF_INTC_ICR46_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR47 */
+#define MCF_INTC_ICR47_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR48 */
+#define MCF_INTC_ICR48_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR49 */
+#define MCF_INTC_ICR49_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR50 */
+#define MCF_INTC_ICR50_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR51 */
+#define MCF_INTC_ICR51_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR52 */
+#define MCF_INTC_ICR52_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR53 */
+#define MCF_INTC_ICR53_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR54 */
+#define MCF_INTC_ICR54_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR55 */
+#define MCF_INTC_ICR55_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR56 */
+#define MCF_INTC_ICR56_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR57 */
+#define MCF_INTC_ICR57_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR58 */
+#define MCF_INTC_ICR58_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR59 */
+#define MCF_INTC_ICR59_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR60 */
+#define MCF_INTC_ICR60_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR61 */
+#define MCF_INTC_ICR61_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR62 */
+#define MCF_INTC_ICR62_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for ICR63 */
+#define MCF_INTC_ICR63_IL(x) (((x)&0x07))
+
+/* Bit definitions and macros for SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for LIACK group */
+#define MCF_INTC_LIACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L1IACK */
+#define MCF_INTC_L1IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L2IACK */
+#define MCF_INTC_L2IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L3IACK */
+#define MCF_INTC_L3IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L4IACK */
+#define MCF_INTC_L4IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L5IACK */
+#define MCF_INTC_L5IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L6IACK */
+#define MCF_INTC_L6IACK_VECTOR(x) (x)
+
+/* Bit definitions and macros for L7IACK */
+#define MCF_INTC_L7IACK_VECTOR(x) (x)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_INTC_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_pm.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_PM_H__
+#define __MCF5441X_PM_H__
+
+/*********************************************************************
+*
+* Power Management Module Register Definition
+*
+*********************************************************************/
+
+#define MCF_PM_WCR MCF_REG08(0xFC040013)
+#define MCF_PM_PPMSR0 MCF_REG08(0xFC04002C)
+#define MCF_PM_PPMCR0 MCF_REG08(0xFC04002D)
+#define MCF_PM_PPMSR1 MCF_REG08(0xFC04002E)
+#define MCF_PM_PPMCR1 MCF_REG08(0xFC04002F)
+#define MCF_PM_PPMHR0 MCF_REG32(0xFC040030)
+#define MCF_PM_PPMLR0 MCF_REG32(0xFC040034)
+#define MCF_PM_PPMHR1 MCF_REG32(0xFC040038)
+#define MCF_PM_PPMLR1 MCF_REG32(0xFC04003C)
+#define MCF_PM_LPCR MCF_REG08(0xEC090007)
+#define MCF_PM_MISCCR MCF_REG16(0xEC09000E)
+#define MCF_PM_CDHR MCF_REG16(0xEC090010)
+#define MCF_PM_CDLR MCF_REG16(0xEC090012)
+
+#endif
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_rtc.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Lanttor.Guo@freescale.com
+ *
+ * Description:
+ * This file is the register definition of m5441x RTC module
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __MCF5441X_RTC_H__
+#define __MCF5441X_RTC_H__
+
+/*********************************************************************
+*
+* Real-time Clock (RTC)
+*
+*********************************************************************/
+#ifndef MCFINT_VECBASE
+#define MCFINT_VECBASE 64
+#endif
+
+#define MCFSIM_ICR_RTC (0xFC050040 + 26)
+
+/* Register read/write macros */
+#define MCF_RTC_YEARMON 0xFC0A8000
+#define MCF_RTC_DAYS 0xFC0A8002
+#define MCF_RTC_HOURMIN 0xFC0A8004
+#define MCF_RTC_SECONDS 0xFC0A8006
+#define MCF_RTC_ALRM_YRMON 0xFC0A8008
+#define MCF_RTC_ALRM_DAYS 0xFC0A800A
+#define MCF_RTC_ALRM_HM 0xFC0A800C
+#define MCF_RTC_ALRM_SEC 0xFC0A800E
+#define MCF_RTC_CR 0xFC0A8010
+#define MCF_RTC_SR 0xFC0A8012
+#define MCF_RTC_ISR 0xFC0A8014
+#define MCF_RTC_IER 0xFC0A8016
+#define MCF_RTC_COUNT_DN 0xFC0A8018
+#define MCF_RTC_CFG_DATA 0xFC0A8020
+#define MCF_RTC_DST_HOUR 0xFC0A8022
+#define MCF_RTC_DST_MON 0xFC0A8024
+#define MCF_RTC_DST_DAY 0xFC0A8026
+#define MCF_RTC_COMPEN 0xFC0A8028
+#define MCF_RTC_UP_CNTRH 0xFC0A8032
+#define MCF_RTC_UP_CNTRL 0xFC0A8034
+
+#define MCF_RTC_STANDBY_RAM_START 0xFC0A8040
+#define MCF_RTC_STANDBY_RAM_END 0xFC0A8040
+
+/* Bit definitions and macros for MCF_RTC_YEARMON */
+
+#define MCF_RTC_YEARMON_YEAR_RD(x) (((x) & 0xFF00) >> 8)
+#define MCF_RTC_YEARMON_MON_RD(x) ((x) & 0x00FF)
+#define MCF_RTC_YEARMON_YEAR_SET(x) (((x) & 0x00FF) << 8)
+#define MCF_RTC_YEARMON_MON_SET(x) ((x) & 0x000F)
+
+/* Bit definitions and macros for MCF_RTC_DAYS */
+#define MCF_RTC_DAYS_DAYWEEK_RD(x) (((x) & 0xFF00) >> 8)
+#define MCF_RTC_DAYS_DAY_RD(x) ((x) & 0x00FF)
+#define MCF_RTC_DAYS_DAYWEEK_SET(x) (((x) & 0x0007) << 8)
+#define MCF_RTC_DAYS_DAY_SET(x) ((x) & 0x001F)
+
+/* Bit definitions and macros for MCF_RTC_HOURMIN */
+#define MCF_RTC_HOURMIN_HOURS_RD(x) (((x) & 0xFF00) >> 8)
+#define MCF_RTC_HOURMIN_MINUTES_RD(x) ((x) & 0x00FF)
+#define MCF_RTC_HOURMIN_HOURS_SET(x) (((x) & 0x001F) << 8)
+#define MCF_RTC_HOURMIN_MINUTES_SET(x) ((x) & 0x003F)
+
+/* Bit definitions and macros for MCF_RTC_SECONDS */
+#define MCF_RTC_SECONDS_SECONDS_RD(x) ((x) & 0x00FF)
+#define MCF_RTC_SECONDS_SECONDS_SET(x) (((x) & 0x003F) << 0)
+
+/* Bit definitions and macros for MCF_RTC_CR */
+#define MCF_RTC_CR_WP 0x0002
+
+/* Bit definitions and macros for MCF_RTC_ISR */
+#define MCF_RTC_ISR_STW 0x0002
+#define MCF_RTC_ISR_ALM 0x0004
+#define MCF_RTC_ISR_DAY 0x0008
+#define MCF_RTC_ISR_HR 0x0010
+#define MCF_RTC_ISR_MIN 0x0020
+#define MCF_RTC_ISR_1HZ 0x0040
+#define MCF_RTC_ISR_2HZ 0x0080
+#define MCF_RTC_ISR_SAM0 0x0100
+#define MCF_RTC_ISR_SAM1 0x0200
+#define MCF_RTC_ISR_SAM2 0x0400
+#define MCF_RTC_ISR_SAM3 0x0800
+#define MCF_RTC_ISR_SAM4 0x1000
+#define MCF_RTC_ISR_SAM5 0x2000
+#define MCF_RTC_ISR_SAM6 0x4000
+#define MCF_RTC_ISR_SAM7 0x8000
+
+/* Bit definitions and macros for MCF_RTC_IER */
+#define MCF_RTC_IER_STW 0x0002
+#define MCF_RTC_IER_ALM 0x0004
+#define MCF_RTC_IER_DAY 0x0008
+#define MCF_RTC_IER_HR 0x0010
+#define MCF_RTC_IER_MIN 0x0020
+#define MCF_RTC_IER_1HZ 0x0040
+#define MCF_RTC_IER_2HZ 0x0080
+#define MCF_RTC_IER_SAM0 0x0100
+#define MCF_RTC_IER_SAM1 0x0200
+#define MCF_RTC_IER_SAM2 0x0400
+#define MCF_RTC_IER_SAM3 0x0800
+#define MCF_RTC_IER_SAM4 0x1000
+#define MCF_RTC_IER_SAM5 0x2000
+#define MCF_RTC_IER_SAM6 0x4000
+#define MCF_RTC_IER_SAM7 0x8000
+
+/* Bit definitions and macros for MCF_RTC_CFG_DATA */
+#define MCF_RTC_CFG_DATA_OSCBYP 0x0010
+#define MCF_RTC_CFG_DATA_OSCEN 0x0008
+
+/* Bit definitions and macros for MCF_RTC_SR */
+#define MCF_RTC_SR_INVALID 0x0001
+#define MCF_RTC_SR_WPE 0x0010
+
+/* Interrupt source */
+#define MCFINT_RTC (64+64+26)
+/*********************************************************************/
+
+#endif
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_scm.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __MCF5441X_SCM_H__
+#define __MCF5441X_SCM_H__
+
+/*********************************************************************
+*
+* System Control Module (SCM)
+*
+*********************************************************************/
+
+/* Core Watchdog(CW) Register read/write macros */
+#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */
+#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */
+
+/* CW Bit definitions and macros for SWCR */
+#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */
+#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */
+#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */
+#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */
+#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */
+
+#define MCF_GPT_MAX_TIMEOUT 17
+/********************************************************************/
+
+#endif /* __MCF5441X_SCM_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_sdramc.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_SDRAMC_H__
+#define __MCF5441X_SDRAMC_H__
+
+/*********************************************************************
+*
+* SDRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+/* SDRAM Mode/Extended Mode Register */
+#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000))
+/* SDRAM Control Register */
+#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004))
+/* SDRAM Configuration Register 1 */
+#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008))
+/* SDRAM Configuration Register 2 */
+#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C))
+/* SDRAM Chip Select Register */
+#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110))
+/* SDRAM Chip Select Register */
+#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114))
+
+/* Parameterized register read/write macros for multiple registers */
+/* SDRAM Chip Select Register */
+#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004)))
+
+/* Bit definitions and macros for SDMR */
+#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
+#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */
+#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
+#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
+#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000)
+#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
+
+/* Bit definitions and macros for SDCR */
+#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
+#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
+#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
+#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
+#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
+/* Periodic Refresh Counter */
+#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16)
+#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
+/* Internal Address Mux Select */
+#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24)
+#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
+#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
+#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
+/* Clock Enable */
+#define MCF_SDRAMC_SDCR_CKE (0x40000000)
+/* SDRAM Mode Register Programming Enable */
+#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
+#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00)
+
+/* Bit definitions and macros for SDCFG1 */
+/* Write Latency */
+#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4)
+/* Refresh to active delay */
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
+/* Precharge to active delay */
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
+/* Active to read/write delay */
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
+/* Read CAS Latency */
+#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20)
+/* Single write to read/write/precharge delay */
+#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24)
+/* Single read to read/write/precharge delay */
+#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for SDCFG2 */
+/* Burst Length */
+#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
+/* Burst read to write delay */
+#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20)
+/* Burst write to read/write/precharge delay */
+#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24)
+/* Burst read to read/precharge delay */
+#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28)
+
+/* Bit definitions and macros for SDCS group */
+/* Chip-Select Size */
+#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F))
+/* Chip-Select Base Address */
+#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20)
+#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
+#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
+#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
+#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
+#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
+#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
+#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
+#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
+#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
+#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
+#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
+#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
+#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
+#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
+#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
+
+/* Bit definitions and macros for SDCS0 */
+/* Chip-Select Size */
+#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F))
+/* Chip-Select Base Address */
+#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20)
+#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000)
+#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000)
+#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013)
+#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014)
+#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015)
+#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016)
+#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017)
+#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018)
+#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019)
+#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A)
+#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B)
+#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C)
+#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D)
+#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E)
+#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F)
+
+/* Bit definitions and macros for SDCS1 */
+/* Chip-Select Size */
+#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F))
+/* Chip-Select Base Address */
+#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20)
+
+/********************************************************************/
+
+#endif /* __MCF5441X_SDRAMC_H__ */
--- /dev/null
+++ b/arch/m68k/include/asm/mcf5441x_xbs.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MCF5441X_XBS_H__
+#define __MCF5441X_XBS_H__
+
+/*
+ * Crossbar Switch (XBS)
+ */
+
+/* Register read/write macros */
+#define MCF_XBS_PRS0 MCF_REG32(0xFC004000) /* DRAM */
+#define MCF_XBS_CRS0 MCF_REG32(0xFC004010)
+#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
+#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
+#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
+#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
+#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
+#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
+#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
+#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
+#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
+#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
+
+/* Priorities */
+#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
+#define MCF_XBS_PRI_2 1 /* Level 2 */
+#define MCF_XBS_PRI_3 2 /* Level 3 */
+#define MCF_XBS_PRI_4 3 /* Level 4 */
+#define MCF_XBS_PRI_5 4 /* Level 5 */
+#define MCF_XBS_PRI_6 5 /* Level 6 */
+#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
+#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
+
+/* Priority Register (PRSn) Defs */
+#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2))
+#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
+#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
+#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
+#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
+#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
+#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
+#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
+#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
+
+/* Control Register (CRSn) Defs */
+#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
+#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
+#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
+#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
+
+/* MCF_XBS_CRS_ARB Defs */
+#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
+#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
+
+/* MCF_XBS_CRS_PCTL Defs */
+#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
+#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
+#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
+
+/* MCF_XBS_CRS_PARK Defs */
+#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
+#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
+#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
+#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
+#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
+#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
+#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
+#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
+
+#endif /* __MCF5441X_XBS_H__ */
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