f40c7533bb
This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43388
88 lines
1.9 KiB
ArmAsm
88 lines
1.9 KiB
ArmAsm
/*
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* Copyright (C) 2012 Gateworks Corporation
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* Chris Lang <clang@gateworks.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#define D_CACHE_LINE_SIZE 32
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.text
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/*
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* R8 - DMA Start Address
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* R9 - DMA Length
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* R10 - DMA Direction
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* R11 - DMA type
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* R12 - fiq_buffer Address
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*/
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.global ox820_fiq_end
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ENTRY(ox820_fiq_start)
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str r8, [r13]
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ldmia r12, {r8, r9, r10}
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and r11, r10, #0x3000000
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and r10, r10, #0xff
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teq r11, #0x1000000
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beq ox820_dma_map_area
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teq r11, #0x2000000
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beq ox820_dma_unmap_area
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/* fall through */
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ox820_dma_flush_range:
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bic r8, r8, #D_CACHE_LINE_SIZE - 1
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1:
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mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
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add r8, r8, #D_CACHE_LINE_SIZE
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cmp r8, r9
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blo 1b
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/* fall through */
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ox820_fiq_exit:
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mov r8, #0
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str r8, [r12, #8]
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mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
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subs pc, lr, #4
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ox820_dma_map_area:
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add r9, r9, r8
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teq r10, #DMA_FROM_DEVICE
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beq ox820_dma_inv_range
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teq r10, #DMA_TO_DEVICE
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bne ox820_dma_flush_range
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/* fall through */
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ox820_dma_clean_range:
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bic r8, r8, #D_CACHE_LINE_SIZE - 1
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1:
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mcr p15, 0, r8, c7, c10, 1 @ clean D line
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add r8, r8, #D_CACHE_LINE_SIZE
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cmp r8, r9
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blo 1b
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b ox820_fiq_exit
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ox820_dma_unmap_area:
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add r9, r9, r8
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teq r10, #DMA_TO_DEVICE
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beq ox820_fiq_exit
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/* fall through */
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ox820_dma_inv_range:
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tst r8, #D_CACHE_LINE_SIZE - 1
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bic r8, r8, #D_CACHE_LINE_SIZE - 1
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mcrne p15, 0, r8, c7, c10, 1 @ clean D line
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tst r9, #D_CACHE_LINE_SIZE - 1
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bic r9, r9, #D_CACHE_LINE_SIZE - 1
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mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
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1:
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mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
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add r8, r8, #D_CACHE_LINE_SIZE
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cmp r8, r9
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blo 1b
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b ox820_fiq_exit
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ox820_fiq_end:
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