307 lines
9.0 KiB
Diff
307 lines
9.0 KiB
Diff
From 2ed6efcef399d15910ff60eef72b4cf8e5265c47 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 31 Mar 2016 02:26:37 +0200
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Subject: [PATCH 62/91] clk: mediatek: Export CPU mux clocks for CPU frequency
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control
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This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
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for intermediate clock source switching.
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Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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---
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drivers/clk/mediatek/Makefile | 2 +-
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drivers/clk/mediatek/clk-cpumux.c | 127 ++++++++++++++++++++++++++++++++
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drivers/clk/mediatek/clk-cpumux.h | 22 ++++++
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drivers/clk/mediatek/clk-mt2701.c | 8 ++
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drivers/clk/mediatek/clk-mt8173.c | 23 ++++++
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include/dt-bindings/clock/mt2701-clk.h | 3 +-
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include/dt-bindings/clock/mt8173-clk.h | 4 +-
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7 files changed, 186 insertions(+), 3 deletions(-)
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create mode 100644 drivers/clk/mediatek/clk-cpumux.c
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create mode 100644 drivers/clk/mediatek/clk-cpumux.h
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diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
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index 5b2b91b..76bfab6 100644
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--- a/drivers/clk/mediatek/Makefile
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+++ b/drivers/clk/mediatek/Makefile
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@@ -1,4 +1,4 @@
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-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
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+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o
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obj-$(CONFIG_RESET_CONTROLLER) += reset.o
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obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
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obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
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diff --git a/drivers/clk/mediatek/clk-cpumux.c b/drivers/clk/mediatek/clk-cpumux.c
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new file mode 100644
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index 0000000..91b5238
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-cpumux.c
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@@ -0,0 +1,127 @@
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+/*
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+ * Copyright (c) 2015 Linaro Ltd.
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+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/slab.h>
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+
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+#include "clk-mtk.h"
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+#include "clk-cpumux.h"
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+
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+struct mtk_clk_cpumux {
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+ struct clk_hw hw;
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+ struct regmap *regmap;
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+ u32 reg;
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+ u32 mask;
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+ u8 shift;
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+};
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+
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+static inline struct mtk_clk_cpumux *to_clk_mux(struct clk_hw *_hw)
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+{
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+ return container_of(_hw, struct mtk_clk_cpumux, hw);
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+}
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+
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+static u8 clk_cpumux_get_parent(struct clk_hw *hw)
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+{
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+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
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+ int num_parents = clk_hw_get_num_parents(hw);
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+ unsigned int val;
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+
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+ regmap_read(mux->regmap, mux->reg, &val);
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+
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+ val >>= mux->shift;
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+ val &= mux->mask;
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+
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+ if (val >= num_parents)
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+ return -EINVAL;
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+
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+ return val;
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+}
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+
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+static int clk_cpumux_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct mtk_clk_cpumux *mux = to_clk_mux(hw);
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+ u32 mask, val;
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+
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+ val = index << mux->shift;
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+ mask = mux->mask << mux->shift;
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+
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+ return regmap_update_bits(mux->regmap, mux->reg, mask, val);
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+}
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+
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+static const struct clk_ops clk_cpumux_ops = {
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+ .get_parent = clk_cpumux_get_parent,
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+ .set_parent = clk_cpumux_set_parent,
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+};
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+
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+static struct clk __init *mtk_clk_register_cpumux(const struct mtk_composite *mux,
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+ struct regmap *regmap)
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+{
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+ struct mtk_clk_cpumux *cpumux;
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+ struct clk *clk;
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+ struct clk_init_data init;
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+
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+ cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
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+ if (!cpumux)
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+ return ERR_PTR(-ENOMEM);
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+
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+ init.name = mux->name;
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+ init.ops = &clk_cpumux_ops;
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+ init.parent_names = mux->parent_names;
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+ init.num_parents = mux->num_parents;
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+ init.flags = mux->flags;
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+
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+ cpumux->reg = mux->mux_reg;
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+ cpumux->shift = mux->mux_shift;
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+ cpumux->mask = BIT(mux->mux_width) - 1;
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+ cpumux->regmap = regmap;
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+ cpumux->hw.init = &init;
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+
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+ clk = clk_register(NULL, &cpumux->hw);
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+ if (IS_ERR(clk))
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+ kfree(cpumux);
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+
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+ return clk;
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+}
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+
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+int __init mtk_clk_register_cpumuxes(struct device_node *node,
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+ const struct mtk_composite *clks, int num,
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+ struct clk_onecell_data *clk_data)
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+{
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+ int i;
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+ struct clk *clk;
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+ struct regmap *regmap;
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+
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+ regmap = syscon_node_to_regmap(node);
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+ if (IS_ERR(regmap)) {
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+ pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
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+ PTR_ERR(regmap));
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+ return PTR_ERR(regmap);
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+ }
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+
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+ for (i = 0; i < num; i++) {
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+ const struct mtk_composite *mux = &clks[i];
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+
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+ clk = mtk_clk_register_cpumux(mux, regmap);
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+ if (IS_ERR(clk)) {
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+ pr_err("Failed to register clk %s: %ld\n",
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+ mux->name, PTR_ERR(clk));
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+ continue;
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+ }
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+
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+ clk_data->clks[mux->id] = clk;
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+ }
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+
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+ return 0;
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+}
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diff --git a/drivers/clk/mediatek/clk-cpumux.h b/drivers/clk/mediatek/clk-cpumux.h
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new file mode 100644
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index 0000000..52c769f
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--- /dev/null
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+++ b/drivers/clk/mediatek/clk-cpumux.h
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@@ -0,0 +1,22 @@
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+/*
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+ * Copyright (c) 2015 Linaro Ltd.
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+ * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __DRV_CLK_CPUMUX_H
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+#define __DRV_CLK_CPUMUX_H
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+
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+int mtk_clk_register_cpumuxes(struct device_node *node,
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+ const struct mtk_composite *clks, int num,
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+ struct clk_onecell_data *clk_data);
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+
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+#endif /* __DRV_CLK_CPUMUX_H */
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diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
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index 1634288..5c37fcb 100644
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--- a/drivers/clk/mediatek/clk-mt2701.c
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+++ b/drivers/clk/mediatek/clk-mt2701.c
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@@ -18,6 +18,7 @@
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#include "clk-mtk.h"
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#include "clk-gate.h"
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+#include "clk-cpumux.h"
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#include <dt-bindings/clock/mt2701-clk.h>
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@@ -465,6 +466,10 @@ static const char * const cpu_parents[] __initconst = {
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"mmpll"
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};
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+static const struct mtk_composite cpu_muxes[] __initconst = {
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+ MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
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+};
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+
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static const struct mtk_composite top_muxes[] __initconst = {
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MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
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0x0040, 0, 3, INVALID_MUX_GATE_BIT),
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@@ -677,6 +682,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
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mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
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clk_data);
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+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
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+ clk_data);
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+
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
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index 227e356..b82c0e2 100644
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--- a/drivers/clk/mediatek/clk-mt8173.c
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+++ b/drivers/clk/mediatek/clk-mt8173.c
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@@ -18,6 +18,7 @@
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#include "clk-mtk.h"
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#include "clk-gate.h"
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+#include "clk-cpumux.h"
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#include <dt-bindings/clock/mt8173-clk.h>
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@@ -526,6 +527,25 @@ static const char * const i2s3_b_ck_parents[] __initconst = {
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"apll2_div5"
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};
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+static const char * const ca53_parents[] __initconst = {
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+ "clk26m",
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+ "armca7pll",
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+ "mainpll",
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+ "univpll"
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+};
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+
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+static const char * const ca57_parents[] __initconst = {
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+ "clk26m",
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+ "armca15pll",
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+ "mainpll",
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+ "univpll"
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+};
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+
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+static const struct mtk_composite cpu_muxes[] __initconst = {
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+ MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2),
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+ MUX(CLK_INFRA_CA57SEL, "infra_ca57_sel", ca57_parents, 0x0000, 2, 2),
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+};
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+
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static const struct mtk_composite top_muxes[] __initconst = {
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/* CLK_CFG_0 */
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MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
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@@ -945,6 +965,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
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clk_data);
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mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
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+ mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
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+ clk_data);
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+
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
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index 50972d1..a6c63b8 100644
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--- a/include/dt-bindings/clock/mt2701-clk.h
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+++ b/include/dt-bindings/clock/mt2701-clk.h
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@@ -217,7 +217,8 @@
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#define CLK_INFRA_PMICWRAP 17
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#define CLK_INFRA_DDCCI 18
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#define CLK_INFRA_CLK_13M 19
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-#define CLK_INFRA_NR 20
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+#define CLK_INFRA_CPUSEL 20
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+#define CLK_INFRA_NR 21
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/* PERICFG */
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diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
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index 7956ba1..c82ed7c 100644
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--- a/include/dt-bindings/clock/mt8173-clk.h
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+++ b/include/dt-bindings/clock/mt8173-clk.h
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@@ -192,7 +192,9 @@
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#define CLK_INFRA_PMICSPI 10
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#define CLK_INFRA_PMICWRAP 11
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#define CLK_INFRA_CLK_13M 12
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-#define CLK_INFRA_NR_CLK 13
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+#define CLK_INFRA_CA53SEL 13
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+#define CLK_INFRA_CA57SEL 14
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+#define CLK_INFRA_NR_CLK 15
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/* PERI_SYS */
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--
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1.7.10.4
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