75 lines
2.5 KiB
Diff
75 lines
2.5 KiB
Diff
From 6610fdbea393a4a8ed956b2aaf7012bea3a5069e Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 31 Mar 2016 06:46:51 +0200
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Subject: [PATCH 61/91] clk: mediatek: enable critical clocks
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/clk/mediatek/clk-mt2701.c | 22 ++++++++++++++++++++--
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1 file changed, 20 insertions(+), 2 deletions(-)
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diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
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index 812b347..1634288 100644
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--- a/drivers/clk/mediatek/clk-mt2701.c
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+++ b/drivers/clk/mediatek/clk-mt2701.c
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@@ -573,6 +573,20 @@ static const struct mtk_gate top_clks[] __initconst = {
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GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
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};
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+static struct clk_onecell_data *mt7623_top_clk_data __initdata;
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+static struct clk_onecell_data *mt7623_pll_clk_data __initdata;
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+
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+static void __init mtk_clk_enable_critical(void)
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+{
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+ if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
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+ return;
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+
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+ clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
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+ clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
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+}
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+
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static void __init mtk_topckgen_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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@@ -585,7 +599,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
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return;
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}
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- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
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+ mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
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mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
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clk_data);
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@@ -606,6 +620,8 @@ static void __init mtk_topckgen_init(struct device_node *node)
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
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+ mtk_clk_enable_critical();
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}
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CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
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@@ -1202,7 +1218,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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struct clk_onecell_data *clk_data;
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int r;
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- clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
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+ mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
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if (!clk_data)
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return;
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@@ -1213,6 +1229,8 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
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+ mtk_clk_enable_critical();
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}
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CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
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mtk_apmixedsys_init);
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--
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1.7.10.4
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