f34397d1b7
The following patches were dropped because they are already applied upstream: - 0038-MIPS-lantiq-fpi-on-ar9.patch - 0039-MIPS-lantiq-initialize-usb-on-boot.patch - 0042-USB-DWC2-big-endian-support.patch - 0043-gpio-stp-xway-fix-phy-mask.patch All other patches were simply refreshed, except the following: - 0001-MIPS-lantiq-add-pcie-driver.patch Changes to arch/mips/lantiq/xway/sysctrl.c (these changes disabled some PMU gates for the vrx200 / VR9 SoCs) were removed since the upstream kernel disables unused PMU gates automatically (since 95135bfa7ead1becc2879230f72583dde2b71a0c "MIPS: Lantiq: Deactivate most of the devices by default"). - 0025-NET-MIPS-lantiq-adds-xrx200-net.patch Since OpenWrt commit 55ba20afcc2fe785146316e5be2c2473cb329885 drivers should use of_get_mac_address(). of_get_mac_address_mtd is not available for drivers anymore since it's called automatically within of_get_mac_address(). - 0028-NET-lantiq-various-etop-fixes.patch Same changes as in 0025-NET-MIPS-lantiq-adds-xrx200-net.patch While refreshing the kernel configuration SPI support had to be moved to config-4.4 because otherwise M25P80 was disabled. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48307
45 lines
1.4 KiB
Diff
45 lines
1.4 KiB
Diff
From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 28 Jul 2013 18:06:39 +0200
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Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
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persistent
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -54,6 +54,8 @@
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#define NAND_CON_CSMUX (1 << 1)
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#define NAND_CON_NANDM 1
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+static u32 xway_latchcmd;
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+
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static void xway_reset_chip(struct nand_chip *chip)
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{
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unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
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unsigned long flags;
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if (ctrl & NAND_CTRL_CHANGE) {
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- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
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if (ctrl & NAND_CLE)
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- nandaddr |= NAND_WRITE_CMD;
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- else
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- nandaddr |= NAND_WRITE_ADDR;
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- this->IO_ADDR_W = (void __iomem *) nandaddr;
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+ xway_latchcmd = NAND_WRITE_CMD;
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+ else if (ctrl & NAND_ALE)
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+ xway_latchcmd = NAND_WRITE_ADDR;
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}
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if (cmd != NAND_CMD_NONE) {
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spin_lock_irqsave(&ebu_lock, flags);
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- writeb(cmd, this->IO_ADDR_W);
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+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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spin_unlock_irqrestore(&ebu_lock, flags);
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