openwrt_archive/target/linux/generic/patches-4.4/810-pci_disable_common_quirks.patch
Jonas Gorski a45fb9ceb3 kernel: add linux 4.4 support
Based on 4.4-rc3. Runtime tested on MIPS.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>

SVN-Revision: 47701
2015-12-02 22:23:22 +00:00

52 lines
1.9 KiB
Diff

--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -68,6 +68,12 @@ config XEN_PCIDEV_FRONTEND
The PCI device frontend driver allows the kernel to import arbitrary
PCI devices from a PCI backend to support PCI driver domains.
+config PCI_DISABLE_COMMON_QUIRKS
+ bool "PCI disable common quirks"
+ depends on PCI
+ help
+ If you don't know what to do here, say N.
+
config HT_IRQ
bool "Interrupts on hypertransport devices"
default y
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -41,6 +41,7 @@ static void quirk_mmio_always_on(struct
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
/* The Mellanox Tavor device gives false positive parity errors
* Mark this device with a broken_parity_status, to allow
* PCI scanning code to "skip" this now blacklisted device.
@@ -2963,6 +2964,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
/*
* Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
@@ -3019,6 +3021,8 @@ static void fixup_debug_report(struct pc
}
}
+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS
+
/*
* Some BIOS implementations leave the Intel GPU interrupts enabled,
* even though no one is handling them (f.e. i915 driver is never loaded).
@@ -3053,6 +3057,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */
+
/*
* PCI devices which are on Intel chips can skip the 10ms delay
* before entering D3 mode.