293 lines
8.3 KiB
C
293 lines
8.3 KiB
C
/*
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* Copyright 2012 Gateworks Corporation
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* Chris Lang <clang@gateworks.com>
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* Tim Harvey <tharvey@gateworks.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/irq.h>
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/*
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* Registers
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*/
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#define GPIO_INPUT 0x04
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#define GPIO_DIR 0x08
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#define GPIO_SET 0x10
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#define GPIO_CLEAR 0x14
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#define GPIO_INTERRUPT_ENABLE 0x20
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#define GPIO_INTERRUPT_RAW_STATUS 0x24
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#define GPIO_INTERRUPT_MASKED_STATUS 0x28
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#define GPIO_INTERRUPT_MASK 0x2C
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#define GPIO_INTERRUPT_CLEAR 0x30
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#define GPIO_INTERRUPT_TRIGGER_METHOD 0x34
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#define GPIO_INTERRUPT_TRIGGER_BOTH_EDGES 0x38
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#define GPIO_INTERRUPT_TRIGGER_TYPE 0x3C
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#define GPIO_INTERRUPT_TRIGGER_METHOD_EDGE 0
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#define GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL 1
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#define GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE 0
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#define GPIO_INTERRUPT_TRIGGER_EDGE_BOTH 1
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#define GPIO_INTERRUPT_TRIGGER_TYPE_RISING 0
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#define GPIO_INTERRUPT_TRIGGER_TYPE_FALLING 1
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#define GPIO_INTERRUPT_TRIGGER_TYPE_HIGH 0
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#define GPIO_INTERRUPT_TRIGGER_TYPE_LOW 1
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struct cns3xxx_gpio_chip {
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struct gpio_chip chip;
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struct irq_domain *domain;
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spinlock_t lock;
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void __iomem *base;
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};
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static struct cns3xxx_gpio_chip cns3xxx_gpio_chips[2];
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static int cns3xxx_gpio_chip_count;
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static inline void
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__set_direction(struct cns3xxx_gpio_chip *cchip, unsigned pin, int input)
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{
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u32 reg;
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reg = __raw_readl(cchip->base + GPIO_DIR);
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if (input)
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reg &= ~(1 << pin);
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else
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reg |= (1 << pin);
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__raw_writel(reg, cchip->base + GPIO_DIR);
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}
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/*
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* GENERIC_GPIO primatives
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*/
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static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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{
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struct cns3xxx_gpio_chip *cchip =
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container_of(chip, struct cns3xxx_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&cchip->lock, flags);
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__set_direction(cchip, pin, 1);
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spin_unlock_irqrestore(&cchip->lock, flags);
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return 0;
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}
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static int cns3xxx_gpio_get(struct gpio_chip *chip, unsigned pin)
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{
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struct cns3xxx_gpio_chip *cchip =
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container_of(chip, struct cns3xxx_gpio_chip, chip);
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int val;
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val = ((__raw_readl(cchip->base + GPIO_INPUT) >> pin) & 0x1);
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return val;
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}
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static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int level)
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{
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struct cns3xxx_gpio_chip *cchip =
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container_of(chip, struct cns3xxx_gpio_chip, chip);
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unsigned long flags;
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spin_lock_irqsave(&cchip->lock, flags);
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if (level)
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__raw_writel(1 << pin, cchip->base + GPIO_SET);
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else
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__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
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__set_direction(cchip, pin, 0);
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spin_unlock_irqrestore(&cchip->lock, flags);
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return 0;
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}
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static void cns3xxx_gpio_set(struct gpio_chip *chip, unsigned pin,
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int level)
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{
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struct cns3xxx_gpio_chip *cchip =
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container_of(chip, struct cns3xxx_gpio_chip, chip);
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if (level)
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__raw_writel(1 << pin, cchip->base + GPIO_SET);
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else
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__raw_writel(1 << pin, cchip->base + GPIO_CLEAR);
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}
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static int cns3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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{
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struct cns3xxx_gpio_chip *cchip =
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container_of(chip, struct cns3xxx_gpio_chip, chip);
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return irq_find_mapping(cchip->domain, pin);
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}
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/*
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* IRQ support
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*/
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/* one interrupt per GPIO controller (GPIOA/GPIOB)
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* this is called in task context, with IRQs enabled
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*/
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static void cns3xxx_gpio_irq_handler(struct irq_desc *desc)
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{
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struct cns3xxx_gpio_chip *cchip = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u16 i;
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u32 reg;
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chained_irq_enter(chip, desc); /* mask and ack the base interrupt */
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/* see which pin(s) triggered the interrupt */
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reg = __raw_readl(cchip->base + GPIO_INTERRUPT_RAW_STATUS);
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for (i = 0; i < 32; i++) {
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if (reg & (1 << i)) {
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/* let the generic IRQ layer handle an interrupt */
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generic_handle_irq(irq_find_mapping(cchip->domain, i));
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}
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}
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chained_irq_exit(chip, desc); /* unmask the base interrupt */
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}
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static int cns3xxx_gpio_irq_set_type(struct irq_data *d, u32 irqtype)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct cns3xxx_gpio_chip *cchip = gc->private;
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u32 gpio = d->hwirq;
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unsigned long flags;
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u32 method, edges, type;
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spin_lock_irqsave(&cchip->lock, flags);
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method = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
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edges = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
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type = __raw_readl(cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
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method &= ~(1 << gpio);
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edges &= ~(1 << gpio);
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type &= ~(1 << gpio);
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switch(irqtype) {
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case IRQ_TYPE_EDGE_RISING:
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method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
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type |= (GPIO_INTERRUPT_TRIGGER_TYPE_RISING << gpio);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_SINGLE << gpio);
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type |= (GPIO_INTERRUPT_TRIGGER_TYPE_FALLING << gpio);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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method |= (GPIO_INTERRUPT_TRIGGER_METHOD_EDGE << gpio);
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edges |= (GPIO_INTERRUPT_TRIGGER_EDGE_BOTH << gpio);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
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type |= (GPIO_INTERRUPT_TRIGGER_TYPE_LOW << gpio);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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method |= (GPIO_INTERRUPT_TRIGGER_METHOD_LEVEL << gpio);
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type |= (GPIO_INTERRUPT_TRIGGER_TYPE_HIGH << gpio);
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break;
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default:
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printk(KERN_WARNING "No irq type\n");
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spin_unlock_irqrestore(&cchip->lock, flags);
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return -EINVAL;
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}
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__raw_writel(method, cchip->base + GPIO_INTERRUPT_TRIGGER_METHOD);
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__raw_writel(edges, cchip->base + GPIO_INTERRUPT_TRIGGER_BOTH_EDGES);
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__raw_writel(type, cchip->base + GPIO_INTERRUPT_TRIGGER_TYPE);
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spin_unlock_irqrestore(&cchip->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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irq_set_handler_locked(d, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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irq_set_handler_locked(d, handle_edge_irq);
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return 0;
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}
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void __init cns3xxx_gpio_init(int gpio_base, int ngpio,
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u32 base, int irq, int secondary_irq_base)
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{
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struct cns3xxx_gpio_chip *cchip;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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char gc_label[16];
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int irq_base;
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if (cns3xxx_gpio_chip_count == ARRAY_SIZE(cns3xxx_gpio_chips))
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return;
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snprintf(gc_label, sizeof(gc_label), "cns3xxx_gpio%d",
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cns3xxx_gpio_chip_count);
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cchip = cns3xxx_gpio_chips + cns3xxx_gpio_chip_count;
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cchip->chip.label = kstrdup(gc_label, GFP_KERNEL);
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cchip->chip.direction_input = cns3xxx_gpio_direction_input;
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cchip->chip.get = cns3xxx_gpio_get;
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cchip->chip.direction_output = cns3xxx_gpio_direction_output;
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cchip->chip.set = cns3xxx_gpio_set;
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cchip->chip.to_irq = cns3xxx_gpio_to_irq;
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cchip->chip.base = gpio_base;
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cchip->chip.ngpio = ngpio;
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cchip->chip.can_sleep = 0;
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spin_lock_init(&cchip->lock);
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cchip->base = (void __iomem *)base;
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BUG_ON(gpiochip_add(&cchip->chip) < 0);
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cns3xxx_gpio_chip_count++;
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/* clear GPIO interrupts */
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__raw_writel(0xffff, cchip->base + GPIO_INTERRUPT_CLEAR);
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irq_base = irq_alloc_descs(-1, secondary_irq_base, ngpio,
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numa_node_id());
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if (irq_base < 0)
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goto out_irqdesc_free;
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cchip->domain = irq_domain_add_legacy(NULL, ngpio, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!cchip->domain)
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goto out_irqdesc_free;
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/*
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* IRQ chip init
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*/
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gc = irq_alloc_generic_chip("cns3xxx_gpio_irq", 1, irq_base,
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cchip->base, handle_edge_irq);
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gc->private = cchip;
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ct = gc->chip_types;
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ct->type = IRQ_TYPE_EDGE_FALLING;
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ct->regs.ack = GPIO_INTERRUPT_CLEAR;
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ct->regs.enable = GPIO_INTERRUPT_ENABLE;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_enable = irq_gc_unmask_enable_reg;
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ct->chip.irq_disable = irq_gc_mask_disable_reg;
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ct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;
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ct->handler = handle_edge_irq;
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irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, 0);
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irq_set_chained_handler(irq, cns3xxx_gpio_irq_handler);
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irq_set_handler_data(irq, cchip);
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return;
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out_irqdesc_free:
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irq_free_descs(irq_base, ngpio);
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}
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