4bdc5c7964
This patch introduces support of new boards with ARC cores.
[1] Synopsys SDP board
This is a new-generation development board from Synopsys that
consists of base-board and CPU tile-board (which might have a real
ASIC or FPGA with CPU image).
It sports a lot of DesignWare peripherals like GMAC, USB, SPI, I2C
etc and is intended to be used for early development of ARC-based
products.
[2] nSIM
This is a virtual board implemented in Synopsys proprietary
software simulator (even though available for free for open source
community). This board has only serial port as a peripheral and so
it is meant to be used for runtime testing which is especially
useful during bring-up of new tools and platforms.
What's also important ARC cores are very configurable so there're
many variations of options like cache sizes, their line lengths,
additional hardware blocks like multipliers, dividers etc. And this
board could be used to make sure built software still runs on
different HW configurations.
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
SVN-Revision: 47589
72 lines
1.4 KiB
Plaintext
72 lines
1.4 KiB
Plaintext
/*
|
|
* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
/ {
|
|
model = "Synopsys ARC770 nSIM simulator";
|
|
compatible = "snps,nsim";
|
|
clock-frequency = <80000000>; /* 80 MHZ */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
chosen {
|
|
bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &arcuart0;
|
|
};
|
|
|
|
fpga {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* child and parent address space 1:1 mapped */
|
|
ranges;
|
|
|
|
intc: interrupt-controller {
|
|
compatible = "snps,arc700-intc";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
arcuart0: serial@c0fc1000 {
|
|
compatible = "snps,arc-uart";
|
|
reg = <0xc0fc1000 0x100>;
|
|
interrupts = <5>;
|
|
clock-frequency = <80000000>;
|
|
current-speed = <115200>;
|
|
status = "okay";
|
|
};
|
|
|
|
ethernet@c0fc2000 {
|
|
compatible = "snps,arc-emac";
|
|
reg = <0xc0fc2000 0x3c>;
|
|
interrupts = <6>;
|
|
mac-address = [ 00 11 22 33 44 55 ];
|
|
clock-frequency = <80000000>;
|
|
max-speed = <100>;
|
|
phy = <&phy0>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy0: ethernet-phy@0 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
|
|
arcpmu0: pmu {
|
|
compatible = "snps,arc700-pct";
|
|
};
|
|
};
|
|
};
|