83b22e150e
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some boards. These boards depend on the preset values of u-boot which may differ. This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49071
301 lines
8.5 KiB
Diff
301 lines
8.5 KiB
Diff
--- a/arch/mips/ath79/mach-ap136.c
|
|
+++ b/arch/mips/ath79/mach-ap136.c
|
|
@@ -18,23 +18,29 @@
|
|
*
|
|
*/
|
|
|
|
-#include <linux/pci.h>
|
|
-#include <linux/ath9k_platform.h>
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/ar8216_platform.h>
|
|
|
|
-#include "machtypes.h"
|
|
+#include <asm/mach-ath79/ar71xx_regs.h>
|
|
+
|
|
+#include "common.h"
|
|
+#include "pci.h"
|
|
+#include "dev-ap9x-pci.h"
|
|
#include "dev-gpio-buttons.h"
|
|
+#include "dev-eth.h"
|
|
#include "dev-leds-gpio.h"
|
|
-#include "dev-spi.h"
|
|
+#include "dev-m25p80.h"
|
|
+#include "dev-nfc.h"
|
|
#include "dev-usb.h"
|
|
#include "dev-wmac.h"
|
|
-#include "pci.h"
|
|
+#include "machtypes.h"
|
|
|
|
-#define AP136_GPIO_LED_STATUS_RED 14
|
|
-#define AP136_GPIO_LED_STATUS_GREEN 19
|
|
#define AP136_GPIO_LED_USB 4
|
|
-#define AP136_GPIO_LED_WLAN_2G 13
|
|
#define AP136_GPIO_LED_WLAN_5G 12
|
|
+#define AP136_GPIO_LED_WLAN_2G 13
|
|
+#define AP136_GPIO_LED_STATUS_RED 14
|
|
#define AP136_GPIO_LED_WPS_RED 15
|
|
+#define AP136_GPIO_LED_STATUS_GREEN 19
|
|
#define AP136_GPIO_LED_WPS_GREEN 20
|
|
|
|
#define AP136_GPIO_BTN_WPS 16
|
|
@@ -43,37 +49,39 @@
|
|
#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
|
|
#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
|
|
|
|
-#define AP136_WMAC_CALDATA_OFFSET 0x1000
|
|
-#define AP136_PCIE_CALDATA_OFFSET 0x5000
|
|
+#define AP136_MAC0_OFFSET 0
|
|
+#define AP136_MAC1_OFFSET 6
|
|
+#define AP136_WMAC_CALDATA_OFFSET 0x1000
|
|
+#define AP136_PCIE_CALDATA_OFFSET 0x5000
|
|
|
|
static struct gpio_led ap136_leds_gpio[] __initdata = {
|
|
{
|
|
- .name = "qca:green:status",
|
|
+ .name = "ap136:green:status",
|
|
.gpio = AP136_GPIO_LED_STATUS_GREEN,
|
|
.active_low = 1,
|
|
},
|
|
{
|
|
- .name = "qca:red:status",
|
|
+ .name = "ap136:red:status",
|
|
.gpio = AP136_GPIO_LED_STATUS_RED,
|
|
.active_low = 1,
|
|
},
|
|
{
|
|
- .name = "qca:green:wps",
|
|
+ .name = "ap136:green:wps",
|
|
.gpio = AP136_GPIO_LED_WPS_GREEN,
|
|
.active_low = 1,
|
|
},
|
|
{
|
|
- .name = "qca:red:wps",
|
|
+ .name = "ap136:red:wps",
|
|
.gpio = AP136_GPIO_LED_WPS_RED,
|
|
.active_low = 1,
|
|
},
|
|
{
|
|
- .name = "qca:red:wlan-2g",
|
|
+ .name = "ap136:red:wlan-2g",
|
|
.gpio = AP136_GPIO_LED_WLAN_2G,
|
|
.active_low = 1,
|
|
},
|
|
{
|
|
- .name = "qca:red:usb",
|
|
+ .name = "ap136:red:usb",
|
|
.gpio = AP136_GPIO_LED_USB,
|
|
.active_low = 1,
|
|
}
|
|
@@ -98,59 +106,151 @@ static struct gpio_keys_button ap136_gpi
|
|
},
|
|
};
|
|
|
|
-static struct spi_board_info ap136_spi_info[] = {
|
|
- {
|
|
- .bus_num = 0,
|
|
- .chip_select = 0,
|
|
- .max_speed_hz = 25000000,
|
|
- .modalias = "mx25l6405d",
|
|
- }
|
|
+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
|
|
+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
|
|
+
|
|
+static struct ar8327_platform_data ap136_ar8327_data = {
|
|
+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
|
|
+ .pad6_cfg = &ap136_ar8327_pad6_cfg,
|
|
+ .port0_cfg = {
|
|
+ .force_link = 1,
|
|
+ .speed = AR8327_PORT_SPEED_1000,
|
|
+ .duplex = 1,
|
|
+ .txpause = 1,
|
|
+ .rxpause = 1,
|
|
+ },
|
|
+ .port6_cfg = {
|
|
+ .force_link = 1,
|
|
+ .speed = AR8327_PORT_SPEED_1000,
|
|
+ .duplex = 1,
|
|
+ .txpause = 1,
|
|
+ .rxpause = 1,
|
|
+ },
|
|
};
|
|
|
|
-static struct ath79_spi_platform_data ap136_spi_data = {
|
|
- .bus_num = 0,
|
|
- .num_chipselect = 1,
|
|
+static struct mdio_board_info ap136_mdio0_info[] = {
|
|
+ {
|
|
+ .bus_id = "ag71xx-mdio.0",
|
|
+ .phy_addr = 0,
|
|
+ .platform_data = &ap136_ar8327_data,
|
|
+ },
|
|
};
|
|
|
|
-#ifdef CONFIG_PCI
|
|
-static struct ath9k_platform_data ap136_ath9k_data;
|
|
+static void __init ap136_common_setup(void)
|
|
+{
|
|
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
|
+
|
|
+ ath79_register_m25p80(NULL);
|
|
+
|
|
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
|
|
+ ap136_leds_gpio);
|
|
+ ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
|
|
+ ARRAY_SIZE(ap136_gpio_keys),
|
|
+ ap136_gpio_keys);
|
|
+
|
|
+ ath79_register_usb();
|
|
+ ath79_register_nfc();
|
|
+
|
|
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
|
|
+
|
|
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
|
|
|
|
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
|
|
+ ath79_register_mdio(0, 0x0);
|
|
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
|
|
+
|
|
+ mdiobus_register_board_info(ap136_mdio0_info,
|
|
+ ARRAY_SIZE(ap136_mdio0_info));
|
|
+
|
|
+ /* GMAC0 is connected to the RMGII interface */
|
|
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
|
|
+ ath79_eth0_data.phy_mask = BIT(0);
|
|
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
|
|
+
|
|
+ ath79_register_eth(0);
|
|
+
|
|
+ /* GMAC1 is connected tot eh SGMII interface */
|
|
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
|
|
+ ath79_eth1_data.speed = SPEED_1000;
|
|
+ ath79_eth1_data.duplex = DUPLEX_FULL;
|
|
+
|
|
+ ath79_register_eth(1);
|
|
+}
|
|
+
|
|
+static void __init ap136_010_setup(void)
|
|
{
|
|
- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
|
|
- dev->dev.platform_data = &ap136_ath9k_data;
|
|
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
|
|
|
- return 0;
|
|
+ /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
|
|
+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
|
|
+ ap136_ar8327_pad0_cfg.txclk_delay_en = true;
|
|
+ ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
|
|
+ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
|
|
+ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
|
|
+
|
|
+ /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
|
|
+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
|
|
+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
|
|
+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
|
|
+
|
|
+ ath79_eth0_pll_data.pll_1000 = 0xa6000000;
|
|
+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
|
|
+
|
|
+ ap136_common_setup();
|
|
+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
|
|
}
|
|
|
|
-static void __init ap136_pci_init(u8 *eeprom)
|
|
+MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
|
|
+ "Atheros AP136-010 reference board",
|
|
+ ap136_010_setup);
|
|
+
|
|
+static void __init ap136_020_common_setup(void)
|
|
{
|
|
- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
|
|
- sizeof(ap136_ath9k_data.eeprom_data));
|
|
+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
|
|
+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
|
|
+ ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
|
|
+
|
|
+ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
|
|
+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
|
|
+ ap136_ar8327_pad6_cfg.txclk_delay_en = true;
|
|
+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
|
|
+ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
|
|
+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
|
|
|
|
- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
|
|
- ath79_register_pci();
|
|
+ ath79_eth0_pll_data.pll_1000 = 0x56000000;
|
|
+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
|
|
+
|
|
+ ap136_common_setup();
|
|
}
|
|
-#else
|
|
-static inline void ap136_pci_init(u8 *eeprom) {}
|
|
-#endif /* CONFIG_PCI */
|
|
|
|
-static void __init ap136_setup(void)
|
|
+static void __init ap136_020_setup(void)
|
|
{
|
|
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
|
|
|
|
- ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
|
|
- ap136_leds_gpio);
|
|
- ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
|
|
- ARRAY_SIZE(ap136_gpio_keys),
|
|
- ap136_gpio_keys);
|
|
- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
|
|
- ARRAY_SIZE(ap136_spi_info));
|
|
- ath79_register_usb();
|
|
- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
|
|
- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
|
|
+ ap136_020_common_setup();
|
|
+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
|
|
}
|
|
|
|
-MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
|
|
- "Atheros AP136-010 reference board",
|
|
- ap136_setup);
|
|
+MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
|
|
+ "Atheros AP136-020 reference board",
|
|
+ ap136_020_setup);
|
|
+
|
|
+/*
|
|
+ * AP135-020 is similar to AP136-020, any future AP135 specific init
|
|
+ * code can be added here.
|
|
+ */
|
|
+static void __init ap135_020_setup(void)
|
|
+{
|
|
+ ap136_leds_gpio[0].name = "ap135:green:status";
|
|
+ ap136_leds_gpio[1].name = "ap135:red:status";
|
|
+ ap136_leds_gpio[2].name = "ap135:green:wps";
|
|
+ ap136_leds_gpio[3].name = "ap135:red:wps";
|
|
+ ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
|
|
+ ap136_leds_gpio[5].name = "ap135:red:usb";
|
|
+
|
|
+ ap136_020_common_setup();
|
|
+ ath79_register_pci();
|
|
+}
|
|
+
|
|
+MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
|
|
+ "Atheros AP135-020 reference board",
|
|
+ ap135_020_setup);
|
|
--- a/arch/mips/ath79/Kconfig
|
|
+++ b/arch/mips/ath79/Kconfig
|
|
@@ -16,16 +16,17 @@ config ATH79_MACH_AP121
|
|
Atheros AP121 reference board.
|
|
|
|
config ATH79_MACH_AP136
|
|
- bool "Atheros AP136 reference board"
|
|
+ bool "Atheros AP136/AP135 reference board"
|
|
select SOC_QCA955X
|
|
select ATH79_DEV_GPIO_BUTTONS
|
|
select ATH79_DEV_LEDS_GPIO
|
|
+ select ATH79_DEV_NFC
|
|
select ATH79_DEV_SPI
|
|
select ATH79_DEV_USB
|
|
select ATH79_DEV_WMAC
|
|
help
|
|
Say 'Y' here if you want your kernel to support the
|
|
- Atheros AP136 reference board.
|
|
+ Atheros AP136 or AP135 reference boards.
|
|
|
|
config ATH79_MACH_AP81
|
|
bool "Atheros AP81 reference board"
|