0b4248eaae
The ASUS WL-520gU and some other similar Asus devices have a BCM5354 running at 200MHZ and not at 240 which is the default for this SoC. This fixes #4083. Backport of r34325. SVN-Revision: 34377
45 lines
1.0 KiB
Diff
45 lines
1.0 KiB
Diff
--- a/arch/mips/bcm47xx/time.c
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+++ b/arch/mips/bcm47xx/time.c
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@@ -27,10 +27,14 @@
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#include <linux/ssb/ssb.h>
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#include <asm/time.h>
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#include <bcm47xx.h>
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+#include <nvram.h>
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void __init plat_time_init(void)
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{
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unsigned long hz = 0;
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+ u16 chip_id = 0;
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+ char buf[10];
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+ int len;
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/*
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* Use deterministic values for initial counter interrupt
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@@ -43,15 +47,26 @@ void __init plat_time_init(void)
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#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
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+ chip_id = bcm47xx_bus.ssb.chip_id;
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break;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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case BCM47XX_BUS_TYPE_BCMA:
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hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
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+ chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
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break;
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#endif
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}
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+ if (chip_id == 0x5354) {
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+ len = nvram_getenv("clkfreq", buf, sizeof(buf));
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+ if (len >= 0 && !strncmp(buf, "200", 4))
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+ hz = 100000000;
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+ len = nvram_getenv("hardware_version", buf, sizeof(buf));
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+ if (len >= 0 && !strncmp(buf, "WL520G", 6))
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+ hz = 100000000;
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+
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+ }
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if (!hz)
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hz = 100000000;
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