aa39a43602
This updates 025-bcma_backport.patch and 020-ssb_update.patch to a version of ssb and bcma used in recent wireless-testing. I removed all patches adding serial and nand flash support before doing so to not conflict with the existing flash support in the brcm47xx target. This update was done to easily update the wireless drivers afterwards. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 37261
152 lines
4.6 KiB
Diff
152 lines
4.6 KiB
Diff
--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -27,7 +27,7 @@ static char nvram_buf[NVRAM_SPACE];
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static void early_nvram_init(void)
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{
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#ifdef CONFIG_BCM47XX_SSB
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- struct ssb_mipscore *mcore_ssb;
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+ struct ssb_chipcommon *ssb_cc;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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struct bcma_drv_cc *bcma_cc;
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@@ -42,9 +42,9 @@ static void early_nvram_init(void)
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switch (bcm47xx_bus_type) {
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#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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- mcore_ssb = &bcm47xx_bus.ssb.mipscore;
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- base = mcore_ssb->flash_window;
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- lim = mcore_ssb->flash_window_size;
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+ ssb_cc = &bcm47xx_bus.ssb.chipco;
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+ base = ssb_cc->pflash.window;
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+ lim = ssb_cc->pflash.window_size;
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break;
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#endif
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#ifdef CONFIG_BCM47XX_BCMA
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--- a/arch/mips/bcm47xx/wgt634u.c
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+++ b/arch/mips/bcm47xx/wgt634u.c
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@@ -142,24 +142,24 @@ static int __init wgt634u_init(void)
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if (et0mac[0] == 0x00 &&
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((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
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(et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
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- struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
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+ struct ssb_chipcommon *ccore = &bcm47xx_bus.ssb.chipco;
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printk(KERN_INFO "WGT634U machine detected.\n");
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if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
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gpio_interrupt, IRQF_SHARED,
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- "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
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+ "WGT634U GPIO", ccore)) {
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gpio_direction_input(WGT634U_GPIO_RESET);
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gpio_intmask(WGT634U_GPIO_RESET, 1);
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- ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
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+ ssb_chipco_irq_mask(ccore,
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SSB_CHIPCO_IRQ_GPIO,
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SSB_CHIPCO_IRQ_GPIO);
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}
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- wgt634u_flash_data.width = mcore->flash_buswidth;
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- wgt634u_flash_resource.start = mcore->flash_window;
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- wgt634u_flash_resource.end = mcore->flash_window
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- + mcore->flash_window_size
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+ wgt634u_flash_data.width = ccore->pflash.buswidth;
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+ wgt634u_flash_resource.start = ccore->pflash.window;
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+ wgt634u_flash_resource.end = ccore->pflash.window
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+ + ccore->pflash.window_size
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- 1;
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return platform_add_devices(wgt634u_devices,
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ARRAY_SIZE(wgt634u_devices));
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--- a/drivers/ssb/driver_mipscore.c
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+++ b/drivers/ssb/driver_mipscore.c
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@@ -190,16 +190,34 @@ static void ssb_mips_flash_detect(struct
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{
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struct ssb_bus *bus = mcore->dev->bus;
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- mcore->flash_buswidth = 2;
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- if (ssb_chipco_available(&bus->chipco)) {
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- mcore->flash_window = 0x1c000000;
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- mcore->flash_window_size = 0x02000000;
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+ /* When there is no chipcommon on the bus there is 4MB flash */
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+ if (!ssb_chipco_available(&bus->chipco)) {
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+ pr_info("found parallel flash.\n");
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+ bus->chipco.flash_type = SSB_PFLASH;
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+ bus->chipco.pflash.window = SSB_FLASH1;
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+ bus->chipco.pflash.window_size = SSB_FLASH1_SZ;
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+ bus->chipco.pflash.buswidth = 2;
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+ return;
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+ }
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+
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+ switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
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+ case SSB_CHIPCO_FLASHT_STSER:
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+ case SSB_CHIPCO_FLASHT_ATSER:
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+ pr_info("serial flash not supported.\n");
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+ break;
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+ case SSB_CHIPCO_FLASHT_PARA:
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+ pr_info("found parallel flash.\n");
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+ bus->chipco.flash_type = SSB_PFLASH;
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+ bus->chipco.pflash.window = SSB_FLASH2;
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+ bus->chipco.pflash.window_size = SSB_FLASH2_SZ;
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if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
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- & SSB_CHIPCO_CFG_DS16) == 0)
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- mcore->flash_buswidth = 1;
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- } else {
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- mcore->flash_window = 0x1fc00000;
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- mcore->flash_window_size = 0x00400000;
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+ & SSB_CHIPCO_CFG_DS16) == 0)
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+ bus->chipco.pflash.buswidth = 1;
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+ else
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+ bus->chipco.pflash.buswidth = 2;
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+ break;
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+ default:
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+ pr_err("flash not supported.\n");
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}
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}
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--- a/include/linux/ssb/ssb_driver_chipcommon.h
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+++ b/include/linux/ssb/ssb_driver_chipcommon.h
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@@ -583,6 +583,18 @@ struct ssb_chipcommon_pmu {
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+enum ssb_flash_type {
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+ SSB_PFLASH,
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+};
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+
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+struct ssb_pflash {
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+ u8 buswidth;
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+ u32 window;
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+ u32 window_size;
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+};
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+#endif /* CONFIG_SSB_DRIVER_MIPS */
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+
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struct ssb_chipcommon {
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struct ssb_device *dev;
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u32 capabilities;
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@@ -593,6 +605,12 @@ struct ssb_chipcommon {
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struct ssb_chipcommon_pmu pmu;
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u32 ticks_per_ms;
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u32 max_timer_ms;
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+#ifdef CONFIG_SSB_DRIVER_MIPS
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+ enum ssb_flash_type flash_type;
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+ union {
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+ struct ssb_pflash pflash;
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+ };
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+#endif /* CONFIG_SSB_DRIVER_MIPS */
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};
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static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
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--- a/include/linux/ssb/ssb_driver_mips.h
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+++ b/include/linux/ssb/ssb_driver_mips.h
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@@ -19,10 +19,6 @@ struct ssb_mipscore {
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int nr_serial_ports;
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struct ssb_serial_port serial_ports[4];
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-
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- u8 flash_buswidth;
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- u32 flash_window;
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- u32 flash_window_size;
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};
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extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
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