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cd6dd1c01e
Apart from improved power consumption, this fixes the runtime errors
from the pmdomain driver (failed to set idle on domain '%s')
Backport four clk fixes while at it.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19925
(cherry picked from commit 13db7a0708)
[rebased upon 24.10 branch]
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/19989
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
55 lines
2.5 KiB
Diff
55 lines
2.5 KiB
Diff
From cd8b5366636bdff0449b789fb2d33abb20804255 Mon Sep 17 00:00:00 2001
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From: Heiko Stuebner <heiko.stuebner@cherry.de>
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Date: Sat, 14 Dec 2024 23:48:19 +0100
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Subject: [PATCH] clk: rockchip: rk3588: make refclko25m_ethX critical
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Ethernet phys normally need a 25MHz refclk input. On a lot of boards
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this is done with a dedicated 25MHz crystal. But the rk3588 CRU also
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provides a means for that via the refclko25m_ethX clock outputs that
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can be used for that function.
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The mdio bus normally probes devices on the bus at runtime, by reading
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specific phy registers. This requires the phy to be running and thus
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also being supplied by its reference clock.
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While there exist the possibility and dt-binding to declare these
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input clocks for each phy in the phy-dt-node, this is only relevant
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_after_ the phy has been detected and during the drivers probe-run.
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This results in a chicken-and-egg-problem. The refclks in the CRU are
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running on boot of course, but phy-probing can very well happen after
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clk_disable_unused has run.
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In the past I tried to make clock-handling part of the mdio bus code [0]
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but that wasn't very well received, due to it being specific to OF and
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clocks with the consensus being that resources needed for detection
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need to be enabled before.
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So to make probing ethernet phys using the internal refclks possible,
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make those 2 clocks critical.
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[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/
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Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
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Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -772,10 +772,10 @@ static struct rockchip_clk_branch rk3588
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COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
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RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3588_CLKGATE_CON(5), 3, GFLAGS),
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- COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
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+ COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, CLK_IS_CRITICAL,
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RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
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RK3588_CLKGATE_CON(5), 4, GFLAGS),
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- COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
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+ COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, CLK_IS_CRITICAL,
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RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3588_CLKGATE_CON(5), 5, GFLAGS),
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COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
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