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ad9ecd33cc
Serhii and others have experienced PSGMII link degradation up to point that it actually does not pass packets at all or packets arrive as zeros. This usually happened after a couple of hot reboots. Serhii has managed to track it down to PSGMII calibration not being done properly and has fixed it, so all of the code is Serhii-s work. Signed-off-by: Serhii Serhieiev <adron@mstnt.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
290 lines
10 KiB
C
290 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCA8K_H
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#define __QCA8K_H
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#include <linux/regmap.h>
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#define QCA8K_NUM_PORTS 6
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#define QCA8K_CPU_PORT 0
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#define QCA8K_MAX_MTU 9000
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#define QCA8K_BUSY_WAIT_TIMEOUT 2000
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#define QCA8K_NUM_FDB_RECORDS 2048
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#define QCA8K_PORT_VID_DEF 1
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/* Global control registers */
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#define QCA8K_REG_MASK_CTRL 0x000
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#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
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#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
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#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
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#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
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#define QCA8K_REG_RGMII_CTRL 0x004
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#define QCA8K_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
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#define QCA8K_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
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/* Some kind of CLK selection
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* 0: gcc_ess_dly2ns
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* 1: gcc_ess_clk
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*/
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#define QCA8K_RGMII_CTRL_CLK BIT(10)
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#define QCA8K_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
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#define QCA8K_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
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#define QCA8K_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
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#define QCA8K_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
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#define QCA8K_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
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#define QCA8K_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
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#define QCA8K_REG_MODULE_EN 0x030
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#define QCA8K_MODULE_EN_MIB BIT(0)
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#define QCA8K_REG_MIB 0x034
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#define QCA8K_MIB_FLUSH BIT(24)
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#define QCA8K_MIB_CPU_KEEP BIT(20)
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#define QCA8K_MIB_BUSY BIT(17)
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#define QCA8K_GOL_MAC_ADDR0 0x60
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#define QCA8K_GOL_MAC_ADDR1 0x64
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#define QCA8K_MAX_FRAME_SIZE 0x78
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#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
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#define QCA8K_PORT_STATUS_SPEED_10 0
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#define QCA8K_PORT_STATUS_SPEED_100 0x1
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#define QCA8K_PORT_STATUS_SPEED_1000 0x2
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#define QCA8K_PORT_STATUS_TXMAC BIT(2)
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#define QCA8K_PORT_STATUS_RXMAC BIT(3)
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#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
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#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
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#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
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#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
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#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
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#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
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#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
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#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
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#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
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#define QCA8K_PORT_HDR_CTRL_RX_S 2
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#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
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#define QCA8K_PORT_HDR_CTRL_TX_S 0
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#define QCA8K_PORT_HDR_CTRL_ALL 2
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#define QCA8K_PORT_HDR_CTRL_MGMT 1
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#define QCA8K_PORT_HDR_CTRL_NONE 0
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#define QCA8K_REG_SGMII_CTRL 0x0e0
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#define QCA8K_SGMII_EN_PLL BIT(1)
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#define QCA8K_SGMII_EN_RX BIT(2)
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#define QCA8K_SGMII_EN_TX BIT(3)
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#define QCA8K_SGMII_EN_SD BIT(4)
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#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
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#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
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#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
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#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
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#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
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/* EEE control registers */
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#define QCA8K_REG_EEE_CTRL 0x100
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#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
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/* ACL registers */
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#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
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#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
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#define QCA8K_PORT_VLAN_SVID(x) x
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#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
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#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
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#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
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/* Lookup registers */
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#define QCA8K_REG_ATU_DATA0 0x600
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#define QCA8K_ATU_ADDR2_S 24
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#define QCA8K_ATU_ADDR3_S 16
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#define QCA8K_ATU_ADDR4_S 8
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#define QCA8K_REG_ATU_DATA1 0x604
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#define QCA8K_ATU_PORT_M 0x7f
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#define QCA8K_ATU_PORT_S 16
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#define QCA8K_ATU_ADDR0_S 8
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#define QCA8K_REG_ATU_DATA2 0x608
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#define QCA8K_ATU_VID_M 0xfff
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#define QCA8K_ATU_VID_S 8
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#define QCA8K_ATU_STATUS_M 0xf
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#define QCA8K_ATU_STATUS_STATIC 0xf
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#define QCA8K_REG_ATU_FUNC 0x60c
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#define QCA8K_ATU_FUNC_BUSY BIT(31)
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#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
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#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
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#define QCA8K_ATU_FUNC_FULL BIT(12)
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#define QCA8K_ATU_FUNC_PORT_M 0xf
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#define QCA8K_ATU_FUNC_PORT_S 8
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#define QCA8K_REG_VTU_FUNC0 0x610
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#define QCA8K_VTU_FUNC0_VALID BIT(20)
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#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
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#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
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#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
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#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
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#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
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#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
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#define QCA8K_REG_VTU_FUNC1 0x614
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#define QCA8K_VTU_FUNC1_BUSY BIT(31)
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#define QCA8K_VTU_FUNC1_VID_S 16
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#define QCA8K_VTU_FUNC1_FULL BIT(4)
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#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
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#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
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#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
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#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
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#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
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#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
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#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
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#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
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#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
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#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
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#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
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#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
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#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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#define QCA8K_PORT_LOOKUP_LOOPBACK BIT(21)
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#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
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#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
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#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
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#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
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#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
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#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
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#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
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#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
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#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
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#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
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#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
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#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
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#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
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#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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/* Pkt edit registers */
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#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
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/* L3 registers */
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#define QCA8K_HROUTER_CONTROL 0xe00
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
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#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
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#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
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#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
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#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
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#define QCA8K_HNAT_CONTROL 0xe38
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/* MIB registers */
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#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
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/* IPQ4019 PSGMII PHY registers */
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#define PSGMIIPHY_MODE_CONTROL 0x1b4
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#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
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#define PSGMIIPHY_TX_CONTROL 0x288
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#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
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#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
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#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
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#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
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#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
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#define QCA8K_PSGMII_CALB_NUM 100
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#define MII_QCA8075_SSTATUS 0x11
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#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
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#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
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#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
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#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
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#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
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#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
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#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
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#define QCA8075_MMD7_PKT_GEN_START BIT(13)
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#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
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#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
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#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
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#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
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#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
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#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
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#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
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#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
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#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
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#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
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#define QCA8075_PKT_GEN_PKTS_COUNT 4096
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enum {
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QCA8K_PORT_SPEED_10M = 0,
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QCA8K_PORT_SPEED_100M = 1,
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QCA8K_PORT_SPEED_1000M = 2,
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QCA8K_PORT_SPEED_ERR = 3,
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};
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enum qca8k_fdb_cmd {
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QCA8K_FDB_FLUSH = 1,
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QCA8K_FDB_LOAD = 2,
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QCA8K_FDB_PURGE = 3,
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QCA8K_FDB_NEXT = 6,
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QCA8K_FDB_SEARCH = 7,
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};
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enum qca8k_vlan_cmd {
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QCA8K_VLAN_FLUSH = 1,
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QCA8K_VLAN_LOAD = 2,
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QCA8K_VLAN_PURGE = 3,
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QCA8K_VLAN_REMOVE_PORT = 4,
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QCA8K_VLAN_NEXT = 5,
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QCA8K_VLAN_READ = 6,
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};
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struct ar8xxx_port_status {
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int enabled;
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};
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struct qca8k_priv {
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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struct dsa_switch *ds;
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struct mutex reg_mutex;
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struct device *dev;
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struct dsa_switch_ops ops;
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unsigned int port_mtu[QCA8K_NUM_PORTS];
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/* IPQ4019 specific */
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struct regmap *psgmii;
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bool psgmii_calibrated;
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struct phy_device *psgmii_ethphy;
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};
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struct qca8k_mib_desc {
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unsigned int size;
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unsigned int offset;
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const char *name;
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};
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struct qca8k_fdb {
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u16 vid;
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u8 port_mask;
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u8 aging;
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u8 mac[6];
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};
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#endif /* __QCA8K_H */
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