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be71e16630
Backport H616 DVFS support from linux-next. Tested on the Orange Pi Zero 3 (H618 SoC). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/15600 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
189 lines
4.9 KiB
Diff
189 lines
4.9 KiB
Diff
From 3e057e05b3b281bcc29db573eb51f87ee6b5afc0 Mon Sep 17 00:00:00 2001
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From: Martin Botka <martin.botka@somainline.org>
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Date: Thu, 18 Apr 2024 16:44:07 +0100
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Subject: [PATCH] arm64: dts: allwinner: h616: Add CPU OPPs table
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Add an Operating Performance Points table for the CPU cores to enable
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Dynamic Voltage & Frequency Scaling (DVFS) on the H616.
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The values were taken from the BSP sources. There is a separate OPP set
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seen on some H700 devices, but they didn't really work out in testing, so
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they are not included for now.
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Also add the needed cpu_speed_grade nvmem cell and the cooling cells
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properties, to enable passive cooling.
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Signed-off-by: Martin Botka <martin.botka@somainline.org>
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[Andre: rework to minimise opp-microvolt properties]
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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.../dts/allwinner/sun50i-h616-cpu-opp.dtsi | 115 ++++++++++++++++++
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 8 ++
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2 files changed, 123 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
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@@ -0,0 +1,115 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2023 Martin Botka <martin@somainline.org>
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+
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+/ {
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+ cpu_opp_table: opp-table-cpu {
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+ compatible = "allwinner,sun50i-h616-operating-points";
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+ nvmem-cells = <&cpu_speed_grade>;
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+ opp-shared;
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+
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+ opp-480000000 {
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+ opp-hz = /bits/ 64 <480000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x12>;
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+ };
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+
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+ opp-720000000 {
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+ opp-hz = /bits/ 64 <720000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x0d>;
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+ };
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+
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+ opp-792000000 {
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+ opp-hz = /bits/ 64 <792000000>;
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+ opp-microvolt-speed1 = <900000>;
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+ opp-microvolt-speed4 = <940000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x12>;
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+ };
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+
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+ opp-936000000 {
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+ opp-hz = /bits/ 64 <936000000>;
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+ opp-microvolt = <900000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x0d>;
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt-speed0 = <950000>;
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+ opp-microvolt-speed1 = <940000>;
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+ opp-microvolt-speed2 = <950000>;
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+ opp-microvolt-speed3 = <950000>;
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+ opp-microvolt-speed4 = <1020000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt-speed0 = <1000000>;
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+ opp-microvolt-speed2 = <1000000>;
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+ opp-microvolt-speed3 = <1000000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x0d>;
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+ };
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+
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+ opp-1200000000 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt-speed0 = <1050000>;
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+ opp-microvolt-speed1 = <1020000>;
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+ opp-microvolt-speed2 = <1050000>;
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+ opp-microvolt-speed3 = <1050000>;
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+ opp-microvolt-speed4 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1f>;
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+ };
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+
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+ opp-1320000000 {
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+ opp-hz = /bits/ 64 <1320000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x1d>;
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+ };
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x0d>;
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+ };
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+
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+ opp-1512000000 {
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+ opp-hz = /bits/ 64 <1512000000>;
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+ opp-microvolt-speed1 = <1100000>;
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+ opp-microvolt-speed3 = <1100000>;
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+ clock-latency-ns = <244144>; /* 8 32k periods */
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+ opp-supported-hw = <0x0a>;
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu1 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu2 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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+
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+&cpu3 {
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+ operating-points-v2 = <&cpu_opp_table>;
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+};
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -26,6 +26,7 @@
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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@@ -34,6 +35,7 @@
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ #cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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@@ -42,6 +44,7 @@
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ #cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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@@ -50,6 +53,7 @@
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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+ #cooling-cells = <2>;
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};
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};
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@@ -143,6 +147,10 @@
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ths_calibration: thermal-sensor-calibration@14 {
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reg = <0x14 0x8>;
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};
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+
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+ cpu_speed_grade: cpu-speed-grade@0 {
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+ reg = <0x0 2>;
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+ };
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};
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watchdog: watchdog@30090a0 {
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